Tracking memory modifications at cache line granularity

Patent metadata

Field	Value
Publication number	US-12332786-B2
Application number	US-202418629269-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	May 13, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. The method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. The method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. The method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
receive a base address for a physical memory region;
receive a list of empty log memory buffers;
responsive to determining that a cache line in the physical memory region is in a modified state, store the cache line and metadata associated with the cache line in an active log memory buffer referenced by the list of empty log memory buffers; and
send a status message to a host processor, the status message comprising a session identifier of a logging session.

2. The system of claim 1 , wherein the memory device is further configured to:
receive a synchronization request from the host processor;
send a status request to the host processor;
responsive to determining that the cache line is in the modified state, invalidate the cache line;
append the cache line and the metadata associated with the cache line to the active log memory buffer; and
associate a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.

3. The system of claim 1 , wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the modified cache line.

4. The system of claim 1 , wherein the memory device is further configured to:
store a list of full log memory buffers, wherein the list is visible to the host processor.

5. The system of claim 1 , wherein the system comprises a computer express link (CXL) device and wherein the processing device is a memory controller of the CXL device.

6. The system of claim 5 , wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).

7. The system of claim 1 , wherein the processing device is operatively coupled to the host processor, and an interface between the host processor and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.

8. A method comprising:
receiving, by a processing device, a base address for a physical memory region;
receiving a list of empty log memory buffers;
responsive to determining that a cache line in the physical memory region is in a modified state, storing the cache line and metadata associated with the cache line in an active log memory buffer referenced by the list of empty log memory buffers; and
sending a status message to a host processor, the status message comprising a session identifier of a logging session.

9. The method of claim 8 , further comprising:
receiving a synchronization request from the host processor;
sending a status request to the host processor;
responsive to determining that the cache line is in the modified state, invalidating the cache line;
appending the cache line and the metadata associated with the cache line to the active log memory buffer; and
associating a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.

10. The method of claim 8 , wherein the metadata comprises a cache line status flag indicating whether the cache line is in the modified state and a memory address of the cache line.

11. The method of claim 8 , further comprising:
storing a list of full log memory buffers, wherein the list is visible to the host processor.

12. The method of claim 8 , wherein the processing device is a memory controller of a computer express link (CXL) device.

13. The method of claim 12 , wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).

14. The method of claim 8 , wherein the processing device is operatively coupled to the host processor, and an interface between the host processor and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.

15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:
receive a base address for a physical memory region;
receive a list of empty log memory buffers;
responsive to determining that a cache line in the physical memory region is in a modified state, store the cache line and metadata associated with the cache line in an active log memory buffer referenced by the list of empty log memory buffers; and
send a status message to a host processor, the status message comprising a session identifier of a logging session.

16. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:
receive a synchronization request from the host processor;
send a status request to the host processor;
responsive to determining that the cache line is in the modified state, invalidate the cache line;
append the cache line and the metadata associated with the cache line to the active log memory buffer; and
associate a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.

17. The non-transitory computer-readable storage medium of claim 15 ,
wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the modified cache line.

18. The non-transitory computer-readable storage medium of claim 15 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:
store a list of full log memory buffers, wherein the list is visible to the host processor.

19. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is a memory controller of a computer express link (CXL) device.

20. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is operatively coupled to the host processor, and an interface between the host processor and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.

Assignees

• Micron Technology Inc

Inventors

• Boles David

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F13/1668

  Details of memory controller · CPC title