Memory sub-system LUN bypassing

Patent metadata

Field	Value
Publication number	US-12332776-B2
Application number	US-202218036781-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Sep 1, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.

First claim

What is claimed is:

1. A method, comprising:
assigning a respective initial credit value to each LUN of a block stripe;
performing an erase operation across the block stripe;
reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value;
refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero;
programming to each LUN of the block stripe having a respective reduced credit value greater than zero,
determining that each respective reduced credit value is equal to zero; and
reassigning the respective initial credit value to each LUN of the block stripe where each respective reduced credit value is equal to zero.

2. The method of claim 1 , wherein the respective initial credit values have a plurality of values.

3. The method of claim 2 , wherein the plurality of values is in a range from 10 to 1.

4. The method of claim 1 , further comprising marking each LUN of the block stripe with a respective two-bit marker.

5. The method of claim 4 , wherein a first bit of the two-bit marker indicates if a respective LUN of the block stripe is in permanently unusable state or a not-permanently unusable state.

6. The method of claim 5 , wherein a second bit of the two-bit marker indicates if a respective LUN of the block stripe is in a bypass state or a non-bypass state.

7. An apparatus comprising:
memory system controller including a processor, and a bypass component including logic circuitry configured to perform bypass operations, the bypass component configured to:
assign a respective initial credit value to each LUN of a block stripe;
assign a respective iterational bitmask zero value to each LUN of the block stripe with the respective initial credit value being less than a threshold credit bitmask value;
perform an erase operation across the block stripe;
reduce, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value, wherein each LUN of the block stripe having respective iterational bitmask zero value does not have the respective initial credit value reduced;
refrain from programming to each LUN of the block stripe having a respective iterational bitmask zero value;
refrain from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and
program to each LUN of the block stripe having a respective reduced credit value greater than zero and to each LUN having a respective iterational bitmask non-zero value.

8. The apparatus of claim 7 , wherein the threshold credit bitmask value is ten.

9. The apparatus of claim 7 , wherein the respective iterational bitmask zero values are applied in an iterational sequence.

10. The apparatus of claim 9 , wherein the iterational sequence sequentially includes a second iteration, a fourth iteration, a sixth iteration, an eighth iteration, a tenth iteration, a first iteration, a third iteration, a fifth iteration, a seventh iteration, and a ninth iteration.

11. The apparatus of claim 10 , wherein the iterational sequence is sequentially repeated following the ninth iteration.

12. The apparatus of claim 7 , wherein the respective iterational bitmask zero value provides that a respective two-bit marker for each LUN of the block stripe having the respective iterational bitmask zero value indicates that each LUN of the block stripe having the respective iterational bitmask zero value is in a bypass state.

13. The apparatus of claim 12 , wherein the respective iterational bitmask non-zero value provides that the respective two-bit marker for each LUN of the block stripe having the respective iterational bitmask non-zero value indicates that each LUN of the block stripe having the respective iterational bitmask non-zero value is in a non-bypass state.

14. A system, comprising:
a plurality of memory components arranged to form a stackable cross-gridded array of memory cells that form a memory device; and
a memory system controller including a processing device and a bypass component coupled to the memory device, wherein the processing device and bypass component are is configured to:
assign a respective initial credit value to each LUN of a block stripe, wherein the respective initial credit values include a plurality of different values;
perform an erase operation across the block stripe;
reduce, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value;
refrain from programming to each LUN of the block stripe having a respective reduced credit value equal to zero;
program to each LUN of the block stripe having a respective reduced credit value greater than zero, and
refrain from programming to each LUN of the block stripe having a respective iterational bitmask zero value, which indicates that each LUN of the block stripe having the respective iterational bitmask zero value is in a bypass state.

15. The system of claim 14 , wherein the respective initial credit value of each LUN of the block stripe corresponds to a respective program erase count endurance of each LUN of the block stripe.

16. The system of claim 14 , wherein one or more of the LUNs of the block stripe have a program erase count endurance of 10,000 or greater.

17. The system of claim 14 , wherein one or more of the LUNs of the block stripe have a program erase count endurance of less than 10,000.

Assignees

• Micron Technology Inc

Inventors

• Wei Meng

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title