Method and system for multi-chip operation of radar systems

Patent metadata

Field	Value
Publication number	US-12332376-B2
Application number	US-202418439191-A
Country	US
Kind code	B2
Filing date	Feb 12, 2024
Priority date	Jan 13, 2020
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A multi-chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of circuit chips. The multi-chip MIMO radar system includes a central processor configured to receive data from the plurality of circuit chips. The plurality of circuit chips generates sets of selected range, Doppler, and virtual receiver data. The central processor is operable to process the sets of selected range, Doppler, and virtual receiver data to produce selected range detection and angular resolvability of targets.

First claim

The invention claimed is:

1. A multiple input, multiple output (MIMO) radar system comprising:
a first plurality of transmitters and a first plurality of receivers arranged on a first circuit chip, wherein the transmitters and receivers of the first circuit chip are configured to perform selected range, Doppler, and virtual receiver processing on a first set of data, and wherein the transmitters and receivers of the first circuit chip are configured to select a first subset of data from the first set of data; and
a second plurality of transmitters and a second plurality of receivers arranged on a second circuit chip, wherein the transmitters and receivers of the second circuit chip are configured to perform selected range, Doppler, and virtual receiver processing on a second set of data, and wherein the transmitters and receivers of the first circuit chip are configured to select a second subset of data from the second set of data;
wherein the first circuit chip is configured to perform the selected range, Doppler, and virtual receiver processing independent of the second circuit chip; and
wherein a processor is configured to receive the first and second subsets of data and perform target detection and angle estimation using the first and second subsets of data, and wherein the resulting target detection and angle estimation produced by the processor comprises a higher range detection and/or angular resolution performance as compared to any respective target detection and angle estimation performed by the transmitters and receivers of the respective first and second circuit chips.

2. The MIMO radar system of claim 1 , wherein the first circuit chip and the second circuit chip are each separate system-on-chip radar systems.

3. The MIMO radar system of claim 1 , wherein the first circuit chip and the second circuit are arranged on an integrated circuit chip.

4. The MIMO radar system of claim 1 , wherein the processor is configured to receive range, Doppler, and virtual receiver data from at least one of the first circuit chip and the second circuit chip.

5. The MIMO radar system of claim 4 , wherein the first circuit chip, the second circuit chip, and the processor are arranged on an integrated circuit chip.

6. The MIMO radar system of claim 4 , wherein the processor is configured to control the first circuit chip and the second circuit chip.

7. The MIMO radar system of claim 4 , wherein the processor is operable to control the transmitters and receivers of the first circuit chip and the second circuit chip, such that a selected arrangement of transmitters and/or receivers from the respective first circuit chip and the second circuit chip are used to realize a selected detection range and/or Doppler resolution.

8. The MIMO radar system of claim 7 , wherein the first circuit chip and the second circuit chip comprise a plurality of switches configured to select between receiver antennas such that the first circuit chip and the second circuit chip are each configured to select a respective receiver antenna arrangement.

9. The MIMO radar system of claim 4 further comprising an Ethernet network switch configured to communicatively couple the first circuit chip and the second circuit chip to the processor.

10. The MIMO radar system of claim 4 , wherein the processor is a central processing unit configured to perform target detection and/or angle estimation for a target based upon the selected range, Doppler, and virtual receiver processing from the first circuit chip and/or the second circuit chip.

11. The MIMO radar system of claim 10 , wherein the selected range, Doppler, and virtual receiver processing from the first circuit chip and/or the second circuit chip are intermediate processing results, and wherein the processor is configured to perform final processing based upon the intermediate processing results to perform target detection and angle estimation.

12. A multiple input, multiple output (MIMO) radar system comprising:
a plurality of circuit chips, each configured as a separate system-on-chip radar system;
wherein a first circuit chip of the plurality of circuit chips comprises a first plurality of transmitters and a first plurality of receivers arranged on the first circuit chip, wherein the transmitters and receivers of the first circuit chip are configured to produce a first set of selected range, Doppler, and virtual receiver data;
wherein a second circuit chip of the plurality of circuit chips comprises a second plurality of transmitters and a second plurality of receivers arranged on the second circuit chip, wherein the transmitters and receivers of the second circuit chip are configured to produce a second set of selected range, Doppler, and virtual receiver data; and
a processor configured to receive the first and/or second set of selected range, Doppler, and virtual receiver data from the respective first circuit chip and/or second circuit chip, wherein the processor is further configured to perform target detection and angle estimation;
wherein the first circuit chip is configured to perform the selected range, Doppler, and virtual receiver processing independent of the second circuit chip; and
wherein the first and second circuit chips are configured to perform respective selected target detection and angle estimation to produce the first and second sets of selected range, Doppler, and virtual receiver data, and wherein the selected target detection and angle estimation of the first and second circuit chips comprises a lower range detection and/or angular resolution performance as compared to the target detection and angle estimation of the processor.

13. The radar system of claim 12 further comprising an integrated circuit chip, wherein the first circuit chip and the second circuit chip are arranged on the integrated circuit chip.

14. The radar system of claim 13 , wherein the first circuit chip, the second circuit chip, and the processor are arranged on the integrated circuit chip.

15. The radar system of claim 12 , wherein the processor is configured to control the first circuit chip and the second circuit chip.

16. The radar system of claim 12 , wherein the first circuit chip is configured to select a subset of range, Doppler, and virtual receiver data produced by the transmitters and receivers of the first circuit chip to produce the first set of selected range, Doppler, and virtual receiver data, and wherein the second circuit chip is configured to select a subset of range, Doppler, and virtual receiver data produced by the transmitters and receivers of the second circuit chip to produce the second set of selected range, Doppler, and virtual receiver data.

17. The radar system of claim 16 , wherein the processor is configured to perform target detection and angle estimation from the first and second sets of selected range, Doppler, and virtual receiver data, and wherein the angle estimation comprises azimuth estimation and elevation estimation for the detected target.

18. The radar system of claim 16 , wherein the first and second circuit chips are configured to generate respective virtual receiver arrays, wherein the processor is configured to generate a combined virtual array comprising the virtual receiver arrays of the first and second circuit chips, and wherein the processor is configured to perform target detection and angle of arrival estimation based upon the combined virtual array.

19. The radar system of claim 16 , wherein the processor is configured to use the first and second sets of selected range, Doppler, a

Assignees

• Uhnder Inc

Inventors

• Maher Monier
• Roy Arunesh
• Ali Murtaza
• Bordes Jean Pierre
• Davis Curtis

Classifications

• G01S2013/93272

  in the back of the vehicles · CPC title

• G01S13/42

  Simultaneous measurement of distance and other co-ordinates (indirect measurement G01S13/46) · CPC title

• G01S13/36

  with phase comparison between the received signal and the contemporaneously transmitted signal · CPC title

• G01S2013/93271

  in the front of the vehicles · CPC title

• G01S7/28

  Details of pulse systems · CPC title