Display substrate, method of forming display substrate, and display device

Patent metadata

Field	Value
Publication number	US-12328996-B2
Application number	US-201917254168-A
Country	US
Kind code	B2
Filing date	Nov 29, 2019
Priority date	Nov 29, 2019
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A display substrate, a method of forming a display substrate and a display device are provided. The display substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate; The sub-pixel includes a data line pattern extending in a first direction; an initialization signal line pattern including a portion extending in a second direction, the second direction intersecting the first direction, the initialization signal line pattern configured to transmit an initialization signal having a fixed potential; a sub-pixel driving circuit including a driving transistor, a first transistor coupled to a gate of the driving transistor, and a first shielding member coupled to an initialization signal line pattern, an orthographic projection of the first shielding member on a substrate, between the orthographic projection of the first transistor on the substrate and the orthographic projection of the target data line pattern on the substrate; a target data line pattern is included in the next sub-pixel adjacent to the sub-pixel in the second direction.

First claim

What is claimed is:

1. A display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein the sub-pixels comprise:
a data line pattern extending in a first direction;
an initialization signal line pattern comprising a portion extending in a second direction intersecting the first direction, wherein the initialization signal line pattern is configured to transmit an initialization signal having a fixed potential; and
a sub-pixel driving circuit comprising a driving transistor, a first transistor coupled to a gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, wherein an orthographic projection of the first shielding member on the substrate is between an orthographic projection of the first transistor on the substrate and an orthographic projection of a target data line pattern on the substrate; the target data line pattern is arranged in a next sub-pixel adjacent to a sub-pixel in the second direction,
wherein the first shielding member is at a different layer from the initialization signal line pattern, an orthographic projection of the first shielding member on the substrate and an orthographic projection of the initialization signal line pattern on the substrate overlap at a first overlapping region, and the first shielding member is coupled to the initialization signal line pattern through a first via-hole in the first overlapping region,
wherein the first transistor comprises:
a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the sixth conductor pattern having a conductivity superior to conductivities of the fourth semiconductor pattern and the fifth semiconductor pattern; and
a third gate pattern and a fourth gate pattern coupled to the third gate pattern,

wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection portion of the fourth semiconductor pattern on the substrate, the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection portion of the fifth semiconductor pattern on the substrate,
wherein an orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate and the orthographic projection of the fourth gate pattern on the substrate,
wherein the sub-pixel driving circuit further comprises a second shielding member provided with the fixed potential, wherein an orthographic projection of the second shielding member on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate, and
wherein the sub-pixel further comprises a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power supply signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line pattern each extends in the second direction, the power supply signal line pattern comprises a portion extending in the first direction.

2. The display substrate according to claim 1 , wherein the plurality of sub-pixels arranged in the array comprise a plurality of rows of sub-pixels, each row of the sub-pixels comprises the sub-pixels arranged in the second direction, and a plurality of initialization signal lines corresponding to the rows of sub-pixels are formed by sequentially coupling the initialization signal line patterns in the same row of sub-pixels;
the first shielding member extends in the first direction and is coupled to at least one of the initialization signal lines.

3. The display substrate according to claim 1 , wherein the first shielding member and the data line pattern are made of a same material.

4. The display substrate according to claim 1 , wherein the display substrate comprises a first interlayer insulating layer, and the first shielding member and the data line pattern are both on a surface of the first interlayer insulating layer away from the substrate.

5. The display substrate according to claim 1 , wherein the sub-pixel driving circuit further comprises a second transistor coupled to a gate of the driving transistor, the second transistor comprises:
a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, the third conductor pattern having a conductivity superior to conductivities of the first semiconductor pattern and the second semiconductor pattern;
a first gate pattern and a second gate pattern, an orthographic projection of the first gate pattern on the substrate at least partially overlapping with an orthographic projection of the first semiconductor pattern on the substrate, an orthographic projection of the second gate pattern on the substrate at least partially overlapping with an orthographic projection of the second semiconductor pattern on the substrate;
wherein an orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate and the orthographic projection of the second gate pattern on the substrate;
the orthographic projection of the third conductor pattern on the substrate at least partially overlaps with an orthographic projection of the initialization signal pattern on the substrate.

6. The display substrate according to claim 5 , wherein the sub-pixel driving circuit further comprises a first extension portion extending from the first semiconductor pattern, a conductivity of the first extension portion is superior to the conductivity of the first semiconductor pattern;
the first extension comprises a first portion, a second portion and a third portion, the first portion and the third portion each extends in the first direction, the second portion extends in the second direction, one end of the second portion is coupled to the first portion, and the other end of the second portion is coupled to the third portion;
an end of the third portion away from the second portion is coupled to the first transistor.

7. The display substrate according to claim 1 , wherein the second shielding member and the first shielding member are in different layers, an orthographic projection of the second shielding member on the substrate and the orthographic projection of the first shielding member on the substrate overlaps at a second overlapping region, and the second shielding member and the first shielding member are coupled through a second via-hole in the second overlapping region.

8. The display substrate according to claim 1 , wherein the second shielding member and the initialization signal line pattern are made of a same material.

9. The display substrate according to claim 1 , wherein the display substrate further comprises a second interlayer insulating layer, the second shielding member and the initialization signal pattern are both on a surface of the second interlayer insulating layer away from the substrate.

10. The display substrate according to claim 9 , wherein the sub-pixel further comprises a power signal line pattern, the power signal line pattern comprising a portion extending in the first direction, the sub-pixel drive circuit further comprises a storage capacitor, a first electrode plate of the storage capacitor is used as a gate of the drive transistor, a second electrode plate of the storage capacitor is coupled to the power signal line pattern, and the sec

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Diao Yongfu
• Chen Chenyu
• Xu Biao

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K71/621

  Providing a shape to conductive layers, e.g. patterning or selective deposition · CPC title

• G09G3/3225

  using an active matrix · CPC title