SPAD pixel

Patent metadata

Field	Value
Publication number	US-12328962-B2
Application number	US-202318386859-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Oct 12, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

First claim

The invention claimed is:

1. An electronic device, comprising:
a processing circuit level comprising a first semiconductor substrate, first transistors formed in and on top of the first semiconductor substrate, a first insulating layer covering the first transistors, a first stack of insulating layers with conductive tracks over the first insulating layer, first vias passing through the first insulating layer to electrically connect the first transistors to the conductive tracks of the first stack of insulating layers, and first metal pads at an upper surface of the first stack of insulating layers and electrically connected to the conductive tracks of the first stack of insulating layers;
a quench circuit level comprising a layer with plural semiconductor regions insulated from one another by insulating regions, second transistors formed in and on top of the plural semiconductor regions, a second insulating layer covering the second transistors, a third insulating layer covering a side of the layer opposite the second insulating layer, a second stack of insulating layers with conductive tracks over the second insulating layer, second vias passing through the second insulating layer to electrically connect the second transistors to the conductive tracks of the second stack of insulating layers, and second metal pads at an upper surface of the second stack of insulating layers and electrically connected to the conductive tracks of the second stack of insulating layers;
wherein a hybrid bond is made between the first metal pads and the upper surface of the first stack of insulating layers and the second metal pads and the upper surface of the second stack of insulating layers;
a SPAD circuit level comprising a second semiconductor substrate with a photodiode region;
wherein a bond is made between the second insulating layer and the SPAD circuit level; and
wherein a third via extends through the second insulating layer, the insulating regions and the third insulating layer to electrically connect the photodiode region to the conductive tracks of the second stack of insulating layers.

2. The electronic device of claim 1 , wherein the layer of the quench circuit level further includes a ground plane positioned between the third insulating layer and each semiconductor region of the plural semiconductor regions.

3. The electronic device of claim 2 , wherein the layer of the quench circuit level further includes an insulating region positioned between each ground plane and each semiconductor region of the plural semiconductor regions.

4. The electronic device of claim 2 , further comprising a connection via that electrically connects each ground plane to the conductive tracks of the second stack of insulating layers.

5. The electronic device of claim 1 , wherein the first transistors formed in and on top of the first semiconductor substrate comprise digital processing circuit transistors.

6. The electronic device of claim 1 , wherein the second transistors formed in and on top of the semiconductor regions comprise transistors for a quench circuit electrically connected to the photodiode region.

7. The electronic device of claim 6 , wherein the second transistors formed in and on top of the semiconductor regions further comprise transistors for a SPAD disabling circuit electrically connected to the photodiode region.

8. The electronic device of claim 1 , wherein the second semiconductor substrate further comprises a pull-up diode electrically connected to the photodiode region.

9. The electronic device of claim 1 , wherein the SPAD circuit level further comprises a fourth insulating layer over the second semiconductor substrate, and wherein the bond between the second insulating layer and the SPAD circuit level comprises a molecular bond between the third and fourth insulating layers.

10. The electronic device of claim 1 , wherein the SPAD circuit level comprises a single SPAD.

11. The electronic device of claim 1 , wherein the SPAD circuit level comprises no electronic component other than a SPAD.

12. The electronic device according to claim 1 , wherein the quench circuit level only comprises circuitry for providing a quench function for a SPAD in the SPAD circuit level.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Res & Dev Ltd
• Stmicroelectronics Res &Development Limited

Inventors

• Guyader Francois
• Pellegrini Sara
• Rae Bruce

Classifications

• H10F39/809 Primary

  of hybrid image sensors · CPC title

• H10F30/225

  the potential barrier working in avalanche mode, e.g. avalanche photodiodes · CPC title

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• G01J2001/4466

  Avalanche · CPC title

• G01J1/44

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title