Layout of integrated circuit

Patent metadata

Field	Value
Publication number	US-12328944-B2
Application number	US-202117517642-A
Country	US
Kind code	B2
Filing date	Nov 2, 2021
Priority date	Sep 28, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

First claim

What is claimed is:

1. An integrated circuit layout, comprising:
a first row of standard cells and a second row of standard cells abutting along a boundary line extending along a first direction;
a first standard cell of the first row of standard cells, comprising:
a first active region having a first conductivity type and comprising an edge extending along the first direction and adjacent to the boundary line;
another first active region having a second conductivity type and at a side of the first active region that is opposite to the boundary line;
a first gate line extending along a second direction, crossing over the first active region and the another first active region, and protruding from the edge of the first active region by a length L1; and
two first dummy gate lines disposed at two sides of the first active region and parallel to the first gate line; and

a second standard cell of the second row of standard cells, comprising:
a second active region having the first conductivity type and comprising an edge extending along the first direction and adjacent to the boundary line;
another second active region having the second conductivity type and at a side of the second active region that is opposite to the boundary line;
a second gate line extending along the second direction, crossing over the second active region and the another second active region, and protruding from the edge of the second active region by a length L2; and

two second dummy gate lines disposed at two sides of the second active region and parallel to the second gate line,
wherein the first direction and the second direction are perpendicular with respect to one another, the two first dummy gate lines and the two second dummy gate lines are respectively away from the boundary line by a same distance S, the first conductivity type and the second conductivity type are opposite, the edge of the first active region is away from the boundary line by a distance D1, the edge of the second active region is away from the boundary line by a distance D2, and the length L1, the length L2, the distance S, the distance D1 and the distance D2 comprise the relationships:
L 1≤ D 1− S;

L 2≤ D 2− S ; and

D 1≠ D 2.

2. The integrated circuit layout according to claim 1 , wherein the first standard cell and the second standard cell have a same cell height along the second direction.

3. The integrated circuit layout according to claim 1 , wherein the length L2 is equal to or larger than the length L1.

4. The integrated circuit layout according to claim 1 , wherein the two first dummy gate lines and the two second dummy gate lines comprise a same dummy gate line length along the second direction.

5. The integrated circuit layout according to claim 1 , wherein a gate line length of the first gate line along the second direction and a dummy gate line length of the two first dummy gate lines along the second direction are the same.

6. The integrated circuit layout according to claim 1 , wherein a gate line length of the second gate line along the second direction is smaller than a dummy gate line length of the two second dummy gate lines along the second direction.

7. The integrated circuit layout according to claim 1 , wherein the first gate line is away from the boundary line by a distance S1, and the second gate line is away from the boundary line by a distance S2, wherein the distance S1 and the distance S2 are equal to or larger than the distance S, respectively.

8. The integrated circuit layout according to claim 1 , wherein the first standard cell comprises a plurality of the first gate lines disposed on the first active region and arranged along the first direction, and the second standard cell comprises a plurality of the second gate lines disposed on the second active region and arranged along the first direction, wherein at least a portion of the first gate lines are aligned to at least a portion of the second gate lines along the second direction.

9. The integrated circuit layout according to claim 8 , wherein line ends of the first gate lines are aligned with each other along the first direction.

10. The integrated circuit layout according to claim 1 , wherein the two first dummy gate lines are aligned to the two second dummy gate lines along the second direction.

Assignees

• United Microelectronics Corp

Inventors

• Chen Ruei-Yau
• Wang Wei-Jen
• Wu Kun-Yuan
• Chen Chien-Fu
• Hsu Chen-Hsien

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/974

  Layout specifications, i.e. inner core regions · CPC title