Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12328887-B2
Application number	US-202117543102-A
Country	US
Kind code	B2
Filing date	Dec 6, 2021
Priority date	Mar 26, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

There is provided a technique capable of reducing turn-on power losses. A semiconductor device includes: a semiconductor substrate including a drift layer; and a base layer, a contact layer, and a source layer which are provided in the semiconductor substrate. A gate portion is provided in a first trench, with a first gate insulation film therebetween. The first trench is in contact with the contact layer, the source layer, the base layer, and the drift layer. The gate portion is provided with a recessed portion with a bottom farther away from the base layer than a side thereof. A first insulation portion is provided in the recessed portion of the gate portion in the first trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having an upper surface and a lower surface and including a drift layer of a first conductivity type provided between the upper and lower surfaces;
a base layer of a second conductivity type provided on the upper surface side of the drift layer in the semiconductor substrate;
a contact layer of the second conductivity type provided selectively on the upper surface side of the drift layer or the base layer in the semiconductor substrate and having an impurity concentration higher than that of the base layer;
a source layer of the first conductivity type provided selectively on the upper surface side of the base layer in the semiconductor substrate and having an impurity concentration higher than that of the drift layer;
a gate portion provided in a first trench, with a first gate insulation film therebetween, the first trench being in contact with the contact layer, the source layer, the base layer, and the drift layer, the gate portion being electrically connected to a gate electrode, the gate portion being provided with a recessed portion with a bottom farther away from the base layer than a side thereof; and
a first insulation portion provided in the recessed portion of the gate portion in the first trench.

2. The semiconductor device according to claim 1 , wherein:
the gate portion includes
a first gate sub-portion, and
a second gate sub-portion connected to the first gate sub-portion in a direction of extension of the first trench as seen in plan view and protruding upwardly above the first gate sub-portion, the second gate sub-portion facing the source layer across the first gate insulation film;
the first gate sub-portion includes the bottom of the recessed portion of the gate portion; and
the second gate sub-portion includes the side of the recessed portion of the gate portion.

3. The semiconductor device according to claim 2 , further comprising
a carrier storage layer provided between the base layer and the drift layer,
wherein an upper part of the first gate sub-portion is positioned below an upper part of the carrier storage layer.

4. The semiconductor device according to claim 3 , wherein
the upper part of the first gate sub-portion is positioned below a lower part of the carrier storage layer.

5. The semiconductor device according to claim 2 , wherein:
the second gate sub-portion faces the contact layer across the first gate insulation film; and
a relational expression Zpk>Zg is satisfied where Zpk is the length of the contact layer as measured in the direction of extension of the first trench as seen in plan view and Zg is the length of the first insulation portion as measured in that direction.

6. The semiconductor device according to claim 2 , wherein:
the first insulation portion faces the source layer; and
a relational expression Zpk<Zg is satisfied where Zpk is the length of the contact layer as measured in the direction of extension of the first trench as seen in plan view and Zg is the length of the first insulation portion as measured in that direction.

7. The semiconductor device according to claim 2 , further comprising
a dummy portion made of polysilicon and provided in the first trench, the dummy portion being insulated from the gate portion and being electrically connected to an emitter electrode.

8. The semiconductor device according to claim 7 , wherein
the dummy portion is insulated from the gate portion by the first insulation portion.

9. The semiconductor device according to claim 7 , wherein
the dummy portion is provided below the gate portion.

10. The semiconductor device according to claim 2 , further comprising
a metal portion provided in the first trench, the metal portion being insulated from the gate portion by the first insulation portion and being electrically connected to an emitter electrode.

11. The semiconductor device according to claim 2 , further comprising:
a carrier storage layer provided between the base layer and the drift layer; and
a metal portion provided in the first trench, the metal portion being insulated from the gate portion by the first insulation portion and being electrically connected to an emitter electrode,
wherein the metal portion is in Schottky contact with at least one of the carrier storage layer and the drift layer.

12. The semiconductor device according to claim 2 , wherein
the first trench as seen in cross section includes:
a first portion in which the first gate sub-portion is positioned; and
a second portion in which the first insulation portion is positioned,
the second portion being wider than the first portion.

13. The semiconductor device according to claim 2 , wherein
the first insulation portion is in contact with part of the semiconductor substrate other than the base layer.

14. The semiconductor device according to claim 2 , further comprising
a metal portion provided in the first trench, the metal portion being insulated from the gate portion by the first insulation portion and being electrically connected to an emitter electrode,
wherein the metal portion is in Schottky contact with part of the semiconductor substrate other than the base layer.

15. The semiconductor device according to claim 2 , further comprising
a second insulation portion provided on the side opposite to the source layer with respect to the second gate sub-portion as seen in plan view and having a width greater than that of the first gate insulation film.

16. The semiconductor device according to claim 2 , wherein:
a protruding portion is provided on a side of the first trench as seen in plan view; and
the first gate sub-portion and the first insulation portion are provided in the protruding portion.

17. The semiconductor device according to claim 16 , wherein
the second gate sub-portion faces the contact layer across the first gate insulation film.

18. The semiconductor device according to claim 2 , wherein
a relational expression L 1 ×W 1 >L 2 ×W 2 is satisfied where L 1 and W 1 are the height and width, respectively, of the first gate sub-portion, and L 2 and W 2 are the height and width, respectively, of the second gate sub-portion.

19. The semiconductor device according to claim 2 , wherein
a lower part of the first gate sub-portion is positioned below a lower part of the second gate sub-portion.

20. The semiconductor device according to claim 2 , wherein
the gate portion further includes
a third gate sub-portion provided on the first gate sub-portion and having a width smaller than those of the first and second gate sub-portions.

21. The semiconductor device according to claim 20 , wherein
the third gate sub-portion is disposed eccentrically to one side of the gate portion as seen in plan view or in cross section.

22. The semiconductor device according to claim 2 , wherein
a relational expression Lpk>Lb is satisfied where Lpk is a distance from the upper surface of the semiconductor substrate to a lower part of the contact layer, and Lb is a distance from the upper surface of the semiconductor substrate to a lower part of the base layer.

23. The semiconductor device according to claim 22 , wherein
a relational expression Lpk>Lg is satisfied where Lpk is the distance from the upper surface of the semiconductor substrate to the lower part of the contact layer, and Lg is a distance from the upper surface of the semiconductor substr

Assignees

• Mitsubishi Electric Corp

Inventors

• Konishi Kazuya
• Soneda Shinya
• Nishi Koichi
• Nitta Tetsuya
• Furukawa Akihiko

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title