Memory system

Patent metadata

Field	Value
Publication number	US-12328873-B2
Application number	US-202418653241-A
Country	US
Kind code	B2
Filing date	May 2, 2024
Priority date	Sep 7, 2017
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

First claim

What is claimed is:

1. A memory system connectable to a host, comprising:
a nonvolatile memory that includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, each of the plurality of blocks including a plurality of word lines, the plurality of blocks including at least a plurality of first blocks, each of the plurality of first blocks storing valid user data; and
a controller electrically connected to the nonvolatile memory and configured to:
at a startup time of the memory system,
instruct the nonvolatile memory to perform a dummy read operation on at least one of the plurality of first blocks;
make sure that the dummy read operation on the at least one of the plurality of first blocks is finished before reading the valid user data therefrom in accordance with a read command received from the host; and
after the dummy read operation on the at least one of the plurality of first blocks is finished, instruct the nonvolatile memory to read the valid user data from the at least one of the plurality of first blocks in accordance with the read command received from the host, wherein

in the dummy read operation, the nonvolatile memory selects at least one of the plurality of blocks that is instructed by the controller, and applies a voltage higher than a ground voltage to each of the plurality of word lines included in the selected at least one of the plurality of blocks.

2. The memory system of claim 1 , wherein
the controller is further configured to, at the startup time of the memory system, instruct the nonvolatile memory to perform the dummy read operation on all of the plurality of first blocks before reading the valid user data therefrom in accordance with a read command received from the host.

3. The memory system of claim 1 , wherein
the plurality of blocks further includes a plurality of second blocks, each of the plurality of second blocks storing management data of the memory system, and
the controller is further configured to, at the startup time of the memory system, instruct the nonvolatile memory to perform the dummy read operation on at least one of the plurality of second blocks.

4. The memory system of claim 3 , wherein
the controller is further configured to:
manage an address conversion table to map a logical address of the valid user data with a physical address of the nonvolatile memory;
store at least part of the address conversion table in the at least one of the plurality of second blocks as the management data; and

at the startup time of the memory system, instruct the nonvolatile memory to perform the dummy read operation on the at least one of the plurality of second blocks, which stores the at least part of the address conversion table.

5. The memory system of claim 4 , wherein
the controller is further configured to, at the startup time of the memory system, instruct the nonvolatile memory to perform the dummy read operation on all of the plurality of second blocks before reading the valid user data from any of the plurality of first blocks.

6. The memory system of claim 3 , wherein
the controller is further configured to determine a priority of the dummy read operation to be performed on the at least one of the plurality of first blocks and the at least one of the plurality of second blocks, based on an instruction received from the host.

7. The memory system of claim 1 , wherein
the controller is further configured to manage an address conversion table to map a logical address of user data with a physical address of the nonvolatile memory, and
the valid user data is user data which is received from the host and managed in the address conversion table by being associated with the logical address.

8. The memory system of claim 1 , wherein
in the dummy read operation, a memory cell transistor connected to each of the plurality of word lines included in the selected one of the plurality of blocks turns on.

9. The memory system of claim 8 , wherein
in the dummy read operation, data stored in the memory cell transistor that turns on is not output to the controller.

10. The memory system of claim 1 , wherein
the dummy read operation includes a first dummy read operation and a second dummy read operation, and the number of blocks selected in one execution is different between the first dummy read operation and the second dummy read operation.

11. A method of controlling a nonvolatile memory in a memory system, the nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, each of the plurality of blocks including a plurality of word lines, the plurality of blocks including at least a plurality of first blocks, each of the plurality of first blocks storing valid user data, the method comprising:
at a startup time of the memory system,
instructing the nonvolatile memory to perform a dummy read operation on at least one of the plurality of first blocks;
making sure that the dummy read operation on the at least one of the plurality of first blocks is finished before reading the valid user data therefrom in accordance with a read command received from a host; and
after the dummy read operation on the at least one of the plurality of first blocks is finished, instructing the nonvolatile memory to read the valid user data from the at least one of the plurality of first blocks in accordance with the read command received from the host, wherein

in the dummy read operation, the nonvolatile memory selects at least one of the plurality of blocks that is instructed, and applies a voltage higher than a ground voltage to each of the plurality of word lines included in the selected at least one of the plurality of blocks.

12. The method of claim 11 , further comprising:
at the startup time of the memory system,
instructing the nonvolatile memory to perform the dummy read operation on all of the plurality of first blocks before reading the valid user data therefrom in accordance with the read command received from the host.

13. The method of claim 11 , wherein
the plurality of blocks further includes a plurality of second blocks, each of the plurality of second blocks storing management data of the memory system, and
the method further comprises:
at the startup time of the memory system, instructing the nonvolatile memory to perform the dummy read operation on at least one of the plurality of second blocks.

14. The method of claim 13 , further comprising:
managing an address conversion table to map a logical address of the valid user data with a physical address of the nonvolatile memory;
storing at least part of the address conversion table in the at least one of the plurality of second blocks as the management data; and
at the startup time of the memory system, instructing the nonvolatile memory to perform the dummy read operation on the at least one of the plurality of second blocks, which stores the at least part of the address conversion table.

15. The method of claim 14 , further comprising:
at the startup time of the memory system,
instructing the nonvolatile memory to perform the dummy read operation on all of the plurality of second blocks before reading the valid user data from any of the plurality of first blocks.

16. The method of claim 13 , further comprising:
determining a priority of the dummy read operation to be performed on the at least one of the plurality of first blocks and the at least one of the plurality of second blocks, based on an instruction received from the host.

17. The m

Assignees

• Kioxia Corp

Inventors

• Amaki Takehiko
• Kojima Yoshihisa
• Hida Toshikatsu
• Sia Marie Grace Izabelle Angeles
• Suzuki Riki
• Asami Shohei

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title