Non-overlapping generation technique for bootstrap switches

Patent metadata

Field	Value
Publication number	US-12328112-B2
Application number	US-202318307441-A
Country	US
Kind code	B2
Filing date	Apr 26, 2023
Priority date	Apr 26, 2023
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

First claim

What is claimed is:

1. A system, comprising:
a bootstrap circuit having an input and an output, comprising:
a boost capacitor having a first terminal and a second terminal;
a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit;
a second transistor;
a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor;
a switch coupled between the output of the bootstrap circuit and a ground; and
a clock path comprising one or more drivers and a delay circuit coupled in series, wherein:
a control input of the switch is coupled to a first node on the clock path located before the delay circuit, and
a gate of the third transistor is coupled to a second node on the clock path located after the delay circuit; and

a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

2. The system of claim 1 , wherein a gate of the second transistor is coupled to a third node on the clock path located before the delay circuit.

3. The system of claim 2 , wherein one of the one or more drivers is between the second node and the third node.

4. The system of claim 2 , wherein:
the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and a supply rail; and
a gate of the fourth transistor is coupled to the third node on the clock path.

5. The system of claim 1 , wherein the delay circuit has a programmable delay.

6. The system of claim 1 , wherein each of the one or more drivers includes a respective inverter.

7. The system claim 1 , wherein:
the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and a supply rail;
the second transistor comprises a first n-type field effect transistor (NFET);
the third transistor comprises a second NFET; and
the fourth transistor comprises a p-type field effect transistor (PFET).

8. The system of claim 1 , wherein the bootstrap circuit further comprises:
a first switch coupled between the first terminal of the boost capacitor and a supply rail;
a second switch coupled between the second terminal of the boost capacitor and a ground;
a third switch coupled between the second terminal of the boost capacitor and the input of the bootstrap circuit; and
a fourth switch coupled between the output of the bootstrap circuit and the ground.

9. A system, comprising:
a bootstrap circuit having an input and an output, comprising:
a boost capacitor having a first terminal and a second terminal;
a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit;
a second transistor;
a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor;
a first switch coupled between the first terminal of the boost capacitor and a supply rail;
a second switch coupled between the second terminal of the boost capacitor and a ground;
a third switch coupled between the second terminal of the boost capacitor and the input of the bootstrap circuit;
a fourth switch coupled between the output of the bootstrap circuit and the ground; and
a clock path comprising one or more drivers and a delay circuit coupled in series, wherein:
a control input of the second switch and a control input of the fourth switch are coupled to a first node on the clock path located before the delay circuit; and
a gate of the third transistor is coupled to a second node on the clock path located after the delay circuit; and

a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

10. The system of claim 9 , wherein a gate of the second transistor is coupled to a third node on the clock path located before the delay circuit.

11. The system of claim 10 , wherein:
the bootstrap circuit further comprises a fourth transistor coupled between the gate of the first transistor and the supply rail; and
a gate of the fourth transistor is coupled to the third node on the clock path.

12. The system of claim 9 , wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the first switch, wherein the voltage boost circuit is configured to boost a voltage at the first node on the clock path to generate a boosted control signal, and output the boosted control signal to the control input of the first switch.

13. The system of claim 8 , wherein the bootstrap circuit further comprises a voltage boost circuit coupled to a control input of the first switch.

14. The system of claim 8 , wherein a control input of the third switch is coupled to the output of the bootstrap circuit.

15. A system, comprising:
a bootstrap circuit having an input and an output, comprising:
a boost capacitor having a first terminal and a second terminal;
a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit;
a second transistor; and
a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor;

a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit;
a buffer; and
a sampling capacitor, wherein the switch transistor is coupled between an output of the buffer and the sampling capacitor.

16. The system of claim 15 , further comprising a receiver coupled to an input of the buffer.

17. The system of claim 16 , wherein the receiver comprises a mixer.

Assignees

• Qualcomm Inc

Inventors

• Sun Lei
• Tang Yongjian
• Ji Honghao

Classifications

• H03K17/063 Primary

  in field-effect transistor switches · CPC title

• H03M1/0836

  of phase error, e.g. jitter · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title