Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12327787-B2
Application number	US-202117447332-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Jun 23, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first stacked body including a plurality of first conductive layers and a plurality of insulating films alternatively stacked in a first direction, the plurality of first conductive layers each including tungsten;
a second stacked body provided adjacent to the first stacked body in a second direction and including a plurality of second conductive layers and the plurality of insulating films alternatively stacked in the first direction, the plurality of second conductive layers being respectively disposed in a same level in the first direction as a corresponding layer of the plurality of first conductive layers, the plurality of second conductive layers including a silicon containing an impurity, the second direction crossing the first direction;
a semiconductor layer extending in the first direction through an inside of the first stacked body;
a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer in the first stacked body;
a plurality of contact plugs respectively provided on a corresponding layer of the plurality of second conductive layers; and
the plurality of first conductive layers, which include the tungsten, are in direct contact on a same plane with the plurality of second conductive layers, which include the silicon containing the impurity, respectively.

2. The semiconductor memory device according to claim 1 , wherein pillar-shaped bodies that are each provided on the corresponding layer of the plurality of second conductive layers in such a manner as to be in contact with the corresponding layer and extend in the first direction are all the plurality of contact plugs.

3. The semiconductor memory device according to claim 1 , wherein the plurality of second conductive layers include polysilicon containing an impurity.

4. The semiconductor memory device according to claim 1 , further comprising a third stacked body provided adjacent to the first stacked body in a third direction and including a plurality of third conductive layers and the plurality of insulating films alternatively stacked in the first direction, the plurality of third conductive layers being respectively disposed in a same level in the first direction as a corresponding layer of the plurality of first conductive layers, the plurality of third conductive layers including silicon containing an impurity, the third direction crossing the first direction and the second direction.

5. The semiconductor memory device according to claim 4 , wherein a pillar-shaped body that is provided on a single third conductive layer of the plurality of third conductive layers in such a manner as to be in contact with the single third conductive layer is not provided on the third stacked body.

6. The semiconductor memory device according to claim 4 , wherein the plurality of third conductive layers include polysilicon containing an impurity.

7. The semiconductor memory device according to claim 1 , wherein no barrier metal is arranged between the plurality of first conductive layers and the plurality of insulating films and between the semiconductor layer and the plurality of insulating films.

8. The semiconductor memory device according to claim 7 , wherein the barrier metal includes titanium nitride.

Assignees

• Kioxia Corp

Inventors

• Shimizu Takashi
• Fukushima Takashi
• Fukumaki Naomi
• Tahara Hiroko
• Ide Kenichi

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title