Memory with error checking and correcting unit

Patent metadata

Field	Value
Publication number	US-12327600-B2
Application number	US-202318393820-A
Country	US
Kind code	B2
Filing date	Dec 22, 2023
Priority date	Sep 18, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.

First claim

The invention claimed is:

1. A memory, comprising a U half bank and a V half bank, wherein each of the U half bank and the V half bank comprises:
a storage array, wherein the storage array comprises a plurality of bit lines, and each of the plurality of bit lines is connected to a plurality of storage cells in the storage array;
a plurality of column select signal units, wherein the plurality of column select signal units are connected to sensitive amplifiers, and the sensitive amplifiers and the plurality of bit lines are disposed in one-to-one correspondence; and
local data buses, wherein the local data buses are divided into local data buses O and local data buses E, and adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit;
wherein each of the U half bank and V half bank is configured by the local data buses O and local data buses E to output both high bit data and low bit data, and wherein the memory further comprises:
a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data, wherein the local data buses O are electrically connected to the first error checking and correcting unit, and the local data buses E are electrically connected to the second error checking and correcting unit; or the local data buses E are electrically connected to the first error checking and correcting unit, and the local data buses O are electrically connected to the second error checking and correcting unit.

2. The memory of claim 1 , wherein data on the adjacent bit lines enters the respective local data bus O and the respective local data bus E, respectively, through the respective sensitive amplifier and the respective column select signal unit.

3. The memory of claim 2 , wherein the plurality of column select signal units are located on opposite sides of the storage array, a respective local data bus O is electrically connected to a bit line of the plurality of bit lines through a respective column select signal unit on one side of the storage array, and a respective local data bus E is electrically connected to another bit line of the plurality of bit lines through a respective column select signal unit on the other side of the storage array.

4. The memory of claim 1 , further comprising:
block data buses E, configured to interact data with the local data buses E; and
block data buses O, configured to interact data with the local data buses O;
wherein the local data buses O are electrically connected to the first error checking and correcting unit through the block data buses O, and the local data buses E are electrically connected to the second error checking and correcting unit through the block data buses E; or the local data buses O are electrically connected to the second error checking and correcting unit through the block data buses O, and the local data buses E are electrically connected to the first error checking and correcting unit through the block data buses E.

5. The memory of claim 4 , further comprising a local switch circuit; wherein the local data buses E are electrically connected to the block data buses E through the local switch circuit, and the local data buses O are electrically connected to the block data buses O through the local switch circuit.

6. The memory of claim 1 , wherein data corresponding to physically adjacent local data buses enters the first error checking and correcting unit and the second error checking and correcting unit respectively.

7. The memory of claim 1 , wherein each of the plurality of column select signal units comprises a gating switch, the gating switch is controlled to be switched on or off by a column select signal; the sensitive amplifier corresponding to the bit line is configured to interact data with a respective local data bus in a case where the gating switch is switched on; and the sensitive amplifier corresponding to the bit line is configured not to interact data with the respective local data bus in a case where the gating switch is switched off.

8. The memory of claim 1 , further comprising:
column decoding circuits configured to generate column select signals;
wherein the column decoding circuits are located on opposite sides of a plurality of the storage arrays of the U half bank and the V half bank respectively, and each of the U half bank and the V half bank corresponds to different column decoding circuits.

9. The memory of claim 1 , wherein the U half bank comprises an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, odd-numbered block data buses are block data buses O, even- numbered block data buses are block data buses E; the block data buses O are connected to the first error checking and correcting unit, and the block data buses E are connected to the second error checking and correcting unit; or the block data buses O are connected to the second error checking and correcting unit, and the block data buses E are connected to the first error checking and correcting unit.

10. The memory of claim 1 , wherein the V half bank comprises an even number of block data buses, the block data buses are sequentially numbered from zero according to natural numbers, odd-numbered block data buses are block data buses O, even- numbered block data buses are block data buses E; the block data buses O are connected to the first error checking and correcting unit, and the block data buses E are connected to the second error checking and correcting unit; or the block data buses O are connected to the second error checking and correcting unit, and the block data buses E are connected to the first error checking and correcting unit.

11. The memory of claim 9 , wherein each of the V half bank and the U half bank comprises a local switch circuit and an even number of local data buses, the even number of local data buses are divided into local data buses O and local data buses E, the local data buses O are connected to the block data buses O through the local switch circuit, and the local data buses E are connected to the block data buses E through the local switch circuit.

12. The memory of claim 9 , wherein a number of the block data buses is 2*4*(16*N), a number of the local data buses is 2*4*M*(16*N); a number of the block data buses O is 4*(16*N), a number of the block data buses E is 4*(16*N); a number of the local data buses O is 4*M*(16*N), a number of the local data buses E is 4*M*(16*N); one of the block data buses O corresponds to M local data buses O, one of the block data buses E corresponds to M local data buses E; and the local data buses are divided into M*(16*N) groups of local data buses O and M*(16*N) groups of local data buses E by taking 4 adjacent local data buses as one group; wherein M and N are natural numbers greater than or equal to 1.

13. The memory of claim 1 , wherein a storage capacity of the U half bank is the same as a storage capacity of the V half bank.

14. The memory of claim 1 , wherein each of the local data buses is connected to an even number of sensitive amplifiers through gating switches, and the even number of sensitive amplifiers and the plurality of bit lines in the memory are disposed in one-to-one correspondence.

15. The memory of claim 14 , wherein output data on two adjacent bit lines enters a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective g

Assignees

• Changxin Memory Tech Inc

Inventors

• Shang Weibing
• Li Hongwen
• Zhang Liang
• Ji Kangling
• Chi Sungsoo
• Wu Daoxun
• Wang Ying

Classifications

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C29/026

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• G11C2029/1204

  Bit line control · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title