Memory device for selecting memory block according to amount of data and operating method of the same

Patent metadata

Field	Value
Publication number	US-12327017-B2
Application number	US-202016736710-A
Country	US
Kind code	B2
Filing date	Jan 7, 2020
Priority date	Nov 6, 2015
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

First claim

What is claimed is:

1. A method of operating a NAND flash memory device including main memory blocks each of which has a same storage capacity, comprising:
receiving first program data to be stored in the NAND flash memory device;
determining an amount of the first program data;
selecting a main memory block among the main memory blocks;
dividing the main memory block into a first sub-memory block and a second sub-memory block according to the amount of the first program data, wherein the first sub-memory block is selected for storing the first program data;
performing a first program operation of the first program data on the first sub-memory block;
receiving second program data to be stored in the NAND flash memory device;
determining an amount of the second program data;
dividing the second sub-memory block in an erase status into a third sub-memory block and a fourth sub-memory block according to the amount of the second program data, wherein the third sub-memory block is selected for storing the second program data; and
performing a second program operation of the second program data on the third sub-memory block.

2. The method according to claim 1 , wherein each of the main memory blocks and each of the first to fourth sub-memory blocks have different addresses.

3. The method according to claim 1 , further comprising generating data amount information according to the amount of the first and second program data.

4. The method according to claim 3 , wherein the first sub-memory block has a storage capacity that is equal to or greater than the amount of the first program data.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title