Supply voltage control systems and methods for integrated circuits

Patent metadata

Field	Value
Publication number	US-12326749-B2
Application number	US-202117351747-A
Country	US
Kind code	B2
Filing date	Jun 18, 2021
Priority date	Jun 18, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

First claim

What is claimed is:

1. A circuit system comprising:
a power control circuit that generates first and second voltage identifiers;
a first voltage regulator circuit that generates a first supply voltage based on the first voltage identifier, wherein the first supply voltage is provided to a first integrated circuit die, and wherein the power control circuit varies the first voltage identifier based on a change in a first metric associated with the first integrated circuit die to cause the first voltage regulator circuit to vary the first supply voltage;
a second voltage regulator circuit that generates a second supply voltage based on the second voltage identifier, wherein the second supply voltage is provided to a second integrated circuit die, wherein the power control circuit varies the second voltage identifier based on a change in a second metric associated with the second integrated circuit die to cause the second voltage regulator circuit to vary the second supply voltage, wherein the first voltage regulator circuit and the second voltage regulator circuit are fully integrated voltage regulators in a field programmable gate array; and
a circuit control system that physically organizes user logic in the field programmable gate array using timing criticality to control the fully integrated voltage regulators through soft logic for power reduction.

2. The circuit system of claim 1 further comprising:
a third voltage regulator circuit that generates a third supply voltage based on a third voltage identifier generated by the power control circuit, wherein the third supply voltage is provided to a third integrated circuit die, and wherein the power control circuit varies the third voltage identifier based on a change in a third metric associated with the third integrated circuit die to cause the third voltage regulator circuit to vary the third supply voltage.

3. The circuit system of claim 1 , wherein the first metric is one of a performance target, a power consumption target, a frequency target, or a workload of the first integrated circuit die.

4. The circuit system of claim 1 , wherein the second metric is one of a performance target, a power consumption target, a frequency target, or a workload of the second integrated circuit die.

5. The circuit system of claim 1 , wherein the first voltage regulator circuit is in the first integrated circuit die, wherein the second voltage regulator circuit is in the second integrated circuit die, and wherein the power control circuit is in a third integrated circuit die.

6. The circuit system of claim 1 , wherein the first voltage regulator circuit and the second voltage regulator circuit are in an integrated circuit package, and wherein the circuit system is a three-dimensional circuit system.

7. The circuit system of claim 1 , wherein the power control circuit varies the first voltage identifier in response to changes in the first metric indicated by control signals generated by the circuit control system to cause the first voltage regulator circuit to vary the first supply voltage until the first metric has reached a first target value,
wherein the power control circuit varies the second voltage identifier in response to changes in the second metric indicated by the control signals to cause the second voltage regulator circuit to vary the second supply voltage until the second metric has reached a second target value, and wherein the circuit control system monitors the first and second metrics.

8. The circuit system of claim 1 , wherein the power control circuit varies the first voltage identifier based on a change in a workload of the first integrated circuit die to cause the first voltage regulator circuit to vary the first supply voltage, and wherein the power control circuit varies the second voltage identifier based on a change in a workload of the second integrated circuit die to cause the second voltage regulator circuit to vary the second supply voltage.

9. A method for adjusting voltages in a circuit system, the method comprising:
generating first and second voltage identifiers using a power control circuit;
generating a first supply voltage based on the first voltage identifier using a first voltage regulator circuit;
providing the first supply voltage to a first integrated circuit die;
varying the first voltage identifier based on a change in a first metric associated with the first integrated circuit die using the power control circuit to cause the first voltage regulator circuit to vary the first supply voltage;
generating a second supply voltage based on the second voltage identifier using a second voltage regulator circuit;
providing the second supply voltage to a second integrated circuit die;
varying the second voltage identifier based on a change in a second metric associated with the second integrated circuit die using the power control circuit to cause the second voltage regulator circuit to vary the second supply voltage, wherein the first voltage regulator circuit and the second voltage regulator circuit are fully integrated voltage regulators in a field programmable gate array; and
physically organizing user logic in the field programmable gate array using timing criticality to control the fully integrated voltage regulators through soft logic for power reduction.

10. The method of claim 9 further comprising:
generating a third voltage identifier using the power control circuit;
generating a third supply voltage based on the third voltage identifier using a third voltage regulator circuit;
providing the third supply voltage to a third integrated circuit die; and
varying the third voltage identifier based on a change in a third metric associated with the third integrated circuit die using the power control circuit to cause the third voltage regulator circuit to vary the third supply voltage.

11. The method of claim 9 , wherein the first metric is one of a performance target, a power consumption target, a frequency target, or a workload of the first integrated circuit die, and wherein the second metric is one of a performance target, a power consumption target, a frequency target, or a workload of the second integrated circuit die.

12. The method of claim 9 , wherein varying the first voltage identifier further comprises varying the first voltage identifier in response to changes in the first metric indicated by control signals generated by a circuit control system to cause the first voltage regulator circuit to vary the first supply voltage until the first metric has reached a first target value.

13. The method of claim 12 , wherein varying the second voltage identifier further comprises varying the second voltage identifier in response to changes in the second metric indicated by the control signals to cause the second voltage regulator circuit to vary the second supply voltage until the second metric has reached a second target value, and wherein the circuit control system monitors the first and second metrics.

14. The method of claim 9 , wherein
physically organizing the user logic in the field programmable gate array using timing criticality to control the fully integrated voltage regulators through the soft logic for power reduction further comprises adjusting the first and the second supply voltages to meet timing requirements of logic serviced by the fully integrated voltage regulators.

15. A circuit system comprising:
a first voltage regulator circuit that generates a first supply voltage; and
a first integrated circuit die that receives the first supply voltage from the first voltage regulator circuit through a first power del

Assignees

• Intel Corp
• Altera Corp

Inventors

• Srinivasan Archanna
• Gutala Ravi
• Weber Scott
• Dasu Aravind
• Iyer Mahesh
• Nurvitadhi Eriko

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title