Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12324340-B2
Application number	US-202418596678-A
Country	US
Kind code	B2
Filing date	Mar 6, 2024
Priority date	Dec 13, 2019
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.

First claim

The invention claimed is:

1. A display substrate, comprising a substrate and a plurality of sub-pixels corresponding to different colors arranged on the substrate, wherein each sub-pixel comprises a pixel driving circuit and an organic electroluminescent diode electrically connected with the pixel driving circuit; wherein
the pixel driving circuit comprises a first transistor, a second transistor and a storage capacitor, a gate electrode of the first transistor is coupled to a first scanning line, a first electrode of the first transistor is coupled to a data line, and a second electrode of the first transistor is coupled to a gate electrode of the second transistor; a first electrode of the second transistor is coupled to a first power supply voltage line, a second electrode of the second transistor is coupled to a first electrode of the organic electroluminescent diode, and a second electrode of the organic electroluminescent diode is coupled to a second power supply voltage line; a first electrode of the storage capacitor is coupled to the gate electrode of the second transistor, a second electrode of the storage capacitor is coupled to the second electrode of the second transistor;
in a direction perpendicular to the substrate, the display substrate comprises a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked;
the metal oxide layer comprises a first pattern as an active layer of the first transistor, a second pattern as an active layer of the second transistor and a capacitor pattern as the first electrode of the storage capacitor; and the metal oxide layer comprises gallium;
the first pattern, the second pattern and the capacitor pattern are disposed in the same layer, and the first pattern and the capacitor pattern are in an integral structure;
the first metal layer comprises a first electrode plate, and there is at least a first overlapping region between an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the capacitor pattern on the substrate to form the first storage capacitor;
the second metal layer comprises a second electrode plate, and there is at least a second overlapping region between an orthographic projection of the second electrode plate on the substrate and the orthographic projection of the capacitor pattern on the substrate to form a second storage capacitor; and
the first electrode plate and the second electrode plate have same potential.

2. The display substrate of claim 1 , wherein there is an overlapping region between an orthographic projection of the second pattern on the substrate and the orthographic projection of the first electrode plate on the substrate.

3. The display substrate of claim 1 , further comprising a gate insulating layer between the first insulating layer and the second insulating layer, wherein a thickness of the gate insulating layer is less than a thickness of the second insulating layer.

4. The display substrate of claim 3 , wherein a thickness of the first insulating layer is less than a sum of thicknesses of the gate insulating layer and the second insulating layer.

5. The display substrate of claim 1 , further comprising a gate metal layer between the first metal layer and the second metal layer, wherein a thickness of the second metal layer is greater than a thickness of the gate metal layer.

6. The display substrate of claim 1 , wherein a channel aspect ratio of the first transistor is less than a channel aspect ratio of the second transistor.

7. The display substrate of claim 1 , wherein a voltage of the first power supply voltage line is greater than a voltage of the second power supply voltage line, a maximum voltage of the data line is less than a maximum voltage of the first scanning line, and the maximum voltage of the data line is less than the voltage of the first power supply voltage line.

8. The display substrate of claim 1 , wherein an orthographic projection of the first pattern on the substrate and the orthographic projection of the capacitor pattern on the substrate are arranged apart, and the orthographic projection of the first pattern on the substrate and the orthographic projection of the first electrode plate on the substrate are arranged apart.

9. The display substrate of claim 1 , wherein the pixel driving circuit further comprises a third transistor, wherein a gate electrode of the third transistor is coupled to a second scanning line, a first electrode of the third transistor is connected with a compensation line, and a second electrode of the third transistor is coupled to the second electrode of the second transistor.

10. The display substrate of claim 9 , wherein the metal oxide layer further comprises a third pattern as an active layer of the third transistor.

11. The display substrate of claim 10 , wherein the second insulating layer covers the first scanning line, the second scanning line, the gate electrode of the first transistor, the gate electrode of the second transistor and the gate electrode of the third transistor; and a plurality of via holes are arranged on the second insulating layer respectively.

12. The display substrate of claim 11 , wherein the second metal layer further comprises the data line, the first power supply voltage line, a source electrode of the first transistor, a drain electrode of the first transistor, a source electrode of the second transistor, a drain electrode of the second transistor, a source electrode of the third transistor, and a drain electrode of the third transistor.

13. The display substrate of claim 12 , wherein the source electrode of the first transistor and the data line are in an integrated structure, the source electrode of the second transistor and the first power supply voltage line are in an integrated structure, and the drain electrode of the second transistor, the drain electrode of the third transistor and the second electrode plate are in an integrated structure.

14. The display substrate of claim 13 , wherein the capacitor pattern, the active layer of the first transistor, the active layer of the second transistor and the active layer of the third transistor are arranged in a same layer, made of a same material and formed by a same patterning process.

15. The display substrate of claim 14 , wherein the second electrode plate, the data line, the first power supply voltage line, the first source electrode, the drain electrode of the first transistor, the source electrode of the second transistor, the drain electrode of the second transistor, the source electrode of the third transistor and the drain electrode of the third transistor are arranged in a same layer, made of a same material and formed by a same patterning process.

16. The display substrate of claim 1 , wherein the metal oxide layer is a single layer, a double layer or a plurality of layers.

17. The display substrate of claim 16 , wherein the metal oxide layer comprises a first oxide layer and a second oxide layer stacked, wherein conductivity of the second oxide layer is lower than that of the first oxide layer, and a band gap of the second oxide layer is greater than that of the first oxide layer.

18. The display substrate of claim 17 , wherein the first oxide layer is configured to be close to the gate electrodes of the first transistor, the second transistor and the third transistor.

19. A display device, comprising the display substrate of claim 1 .

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xu Chen
• Hao Xueguang
• Qiao Yong
• Wu Xinyin

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title