Display panel and display device

Patent metadata

Field	Value
Publication number	US-12324331-B2
Application number	US-202117790623-A
Country	US
Kind code	B2
Filing date	Aug 23, 2021
Priority date	Aug 23, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

Provided is a display panel. The display panel includes: a base substrate, including a display region and a peripheral region adjacent to the display region; a first power trace, disposed in the peripheral region and on a side of the base substrate; a connecting trace, disposed in the peripheral region and on a side of the base substrate; a plurality of signal lines, disposed in the display region and the peripheral region; an insulating layer, disposed in the display region and the peripheral region; and a cathode layer, disposed in the display region and the peripheral region.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate, comprising a display region and a peripheral region adjacent to the display region;
a first power trace, disposed in the peripheral region and on a side of the base substrate, wherein the first power trace is extended along a first direction and configured to receive a first power signal;
a connecting trace, disposed in the peripheral region and on a side of the base substrate, wherein the connecting trace is electrically connected to the first power trace and extended along a second direction, the second direction intersecting the first direction;
a plurality of signal lines, disposed in the display region and the peripheral region, wherein orthographic projections of parts, disposed in the peripheral region, of the plurality of signal lines on the base substrate enclose a plurality of target regions arranged along the second direction, and an orthographic projection of the connecting trace on the base substrate is at least partially overlapped with the plurality of target regions;
an insulating layer, disposed in the display region and the peripheral region, wherein the insulating layer is disposed on a side, distal from the base substrate, of the connecting trace, and the insulating layer is provided with a plurality of first via holes arranged along the second direction; the plurality of first via holes being in one-to-one correspondence with the plurality of target regions, and an orthographic projection of the first via hole on the base substrate being within one corresponding target region; and
a cathode layer, disposed in the display region and the peripheral region, wherein the cathode layer is disposed on a side, distal from the base substrate, of the insulating layer, and the cathode layer is electrically connected to the connecting trace through the plurality of first via holes.

2. The display panel according to claim 1 , wherein a number of the target regions is less than a number of the signal lines.

3. The display panel according to claim 1 , wherein
a distance between a first part of the cathode layer and the base substrate is shorter than a distance between a second part of the cathode layer and the base substrate,
wherein an orthographic projection of the first part of the cathode layer on the base substrate is overlapped with a region where the orthographic projections of the first via holes on the base substrate are; and an orthographic projection of the second part of the cathode layer on the base substrate is overlapped with a region where the orthographic projections of the signal lines on the base substrate are.

4. The display panel according to claim 1 , wherein the plurality of target regions comprise: a first target region, a second target region adjacent to the first target region along the second direction, a third target region, and a fourth target region adjacent to the third target region along the second direction,
wherein a number of the signal lines between the first target region and the second target region is the same as a number of the signal lines between the third target region and the fourth target region.

5. The display panel according to claim 1 , wherein each of the signal lines at least comprises: a first line segment, a second line segment and a third line segment which are sequentially connected; wherein
both the first line segment and the third line segment are extended along the second direction, and the second line segment is extended along a third direction, the third direction intersecting the second direction; and
an orthographic projection of the first line segment on the base substrate is on a side, close to the display region, of the orthographic projections of the plurality of first via holes on the base substrate, an orthographic projection of the third line segment on the base substrate is on a side, distal from the display region, of the orthographic projections of the plurality of first via holes on the base substrate, and an orthographic projection of the second line segment on the base substrate is between the orthographic projections of two adjacent first via holes on the base substrate.

6. The display panel according to claim 1 , wherein the connecting trace comprises a first sub-trace and a second sub-trace which are sequentially laminated along a direction distal from the base substrate, the first sub-trace and the second sub-trace being extended along the second direction; the insulating layer comprises a first insulating layer group and a second insulating layer group; and each first via hole comprises a first via hole group and a second via hole group, the first via hole group being in the first insulating layer group, and the second via hole group being in the second insulating layer group;
wherein the first insulating layer group is disposed between the first sub-trace and the second sub-trace, and the second insulating layer group is disposed on a side, distal from the base substrate, of the second sub-trace; and the first sub-trace is electrically connected to the second sub-trace through the first via hole group, and the second sub-trace is electrically connected to the cathode layer through the second via hole group.

7. The display panel according to claim 6 , further comprising: a transfer structure disposed between the first sub-trace and the second sub-trace; the first insulating layer group comprises: a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are sequentially laminated along the direction distal from the base substrate; the first via hole group comprises: a plurality of first sub via holes, a plurality of second sub via holes and one third sub via hole, wherein
the plurality of first sub via holes are in the first sub-insulating layer, the plurality of second sub via holes are in the second sub-insulating layer, and the third sub via hole is in the third sub-insulating layer; and
the first sub-insulating layer is disposed between the first sub-trace and the transfer structure, and the second sub-insulating layer and the third sub-insulating layer are disposed between the transfer structure and the second sub-trace; and the first sub-trace is electrically connected to the transfer structure through the plurality of first sub via holes, and the transfer structure is electrically connected to the second sub-trace through the plurality of second sub via holes and the third sub via hole.

8. The display panel according to claim 1 , wherein the peripheral region comprises a first region, the first region being on a side of the display region and the first region comprising a first fan-out region and a second fan-out region arranged along a third direction, wherein the first fan-out region is closer to the display region than the second fan-out region is, the third direction intersecting the second direction,
wherein the orthographic projections of the plurality of first via holes on the base substrate are within the first fan-out region and are closer to the second fan-out region than the display region is.

9. The display panel according to claim 8 , wherein the first fan-out region comprises a first fan-out sub-region and a second fan-out sub-region arranged along the second direction, and the plurality of first via holes comprise a plurality of first-type via holes and a plurality of second-type via holes, wherein
orthographic projections of the plurality of first-type via holes on the base substrate are within the first fan-out sub-region, and orthographic projections of the plurality of second-type via holes on the base substrate are within the second fan-out sub-region; and
the plurality of first-type via holes and the plurality

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Xing
• Xu Pan
• Zhang Dacheng
• Han Ying
• Wang Guoying
• Gao Zhan
• Luo Chengyuan
• Chen Yi

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title