Display apparatus including a blocking layer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12324320-B2
Application number	US-202318219828-A
Country	US
Kind code	B2
Filing date	Jul 10, 2023
Priority date	Jan 16, 2019
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A display apparatus includes: a substrate including a display area and a sensor area, wherein the display area includes a first pixel, and the sensor area includes a second pixel and a transmission portion; a sensor configured to transmit a signal through the substrate via the transmission portion, wherein the second pixel includes second thin-film transistor including a semiconductor layer, and wherein a blocking layer is disposed between the sensor and the second thin-film transistor, wherein the blocking layer covers the semiconductor layer.

First claim

What is claimed is:

1. An apparatus comprising:
a display panel comprising a substrate and a first blocking layer; and
a sensor below the display panel,
wherein the display panel comprises:
the substrate comprising a display area and a sensor area, wherein the display area comprises a first pixel, and the sensor area comprises a second pixel, a wiring unit, and a transmission portion; and
the first blocking layer on the substrate,

wherein the sensor is configured to transmit or to receive a signal through the substrate via the transmission portion,
wherein the second pixel comprises an organic light-emitting diode and a first semiconductor layer,
wherein the second pixel is electrically connected to the wiring unit,
wherein the wiring unit and the first semiconductor layer are disposed above the first blocking layer, and the sensor is disposed below the first blocking layer,
wherein the wiring unit includes a plurality of wiring lines spaced apart from each other, and
wherein the first blocking layer covers at least a portion of the plurality of wiring lines and spaces spaced apart between the plurality of wiring lines in a cross sectional view.

2. The apparatus of claim 1 , wherein the first blocking layer is arranged between the sensor disposed below the substrate and the wiring unit disposed above the substrate, in a direction perpendicular to the substrate.

3. The apparatus of claim 1 , wherein a gate electrode is disposed on the first semiconductor layer, and
at least one wiring line of the plurality of wiring lines is arranged on a same layer as the gate electrode.

4. The apparatus of claim 3 , wherein the at least one wiring line comprises at least one wiring line of a previous scan line, a scan line, an initialization voltage line or a light emission control line.

5. The apparatus of claim 1 , wherein the plurality of wiring lines are spaced apart from each other in a direction horizontal to the substrate, and
a width of the first blocking layer is greater than a total width of the plurality of wiring lines.

6. The apparatus of claim 1 , wherein the plurality of wiring lines are spaced apart from each other in a vertical direction of the substrate, and
the first blocking layer covers the plurality of wiring lines that are spaced apart from each other.

7. The apparatus of claim 1 , wherein the wiring unit and the first semiconductor layer are arranged on different layers.

8. The apparatus of claim 7 , wherein the wiring unit is disposed on the first semiconductor layer with an insulating layer therebetween.

9. The apparatus of claim 1 , wherein the first pixel comprises a second semiconductor layer, and
the first blocking layer does not fully cover the whole area of the second semiconductor layer in a top view of the substrate.

10. The apparatus of claim 1 , wherein a second blocking layer is further arranged between the sensor and the first semiconductor layer, and
the second blocking layer fully covers the whole area of the first semiconductor layer in a top view of the substrate.

11. The apparatus of claim 10 , wherein the first blocking layer and the second blocking layer are arranged on a same layer.

12. The apparatus of claim 10 , wherein the second blocking layer is arranged between the sensor disposed below the substrate and the first semiconductor layer disposed above the substrate, in a direction perpendicular to the substrate.

13. The apparatus of claim 10 , wherein the second blocking layer has a same pattern as a pattern of the first semiconductor layer and a width of the pattern of the second blocking layer is greater than a width of the pattern of the first semiconductor layer.

14. The apparatus of claim 4 , wherein the second blocking layer has a different pattern from a pattern of the first semiconductor layer.

15. The apparatus of claim 1 , wherein the first pixel comprises a second semiconductor layer,
a third blocking layer is further arranged between the substrate and the second semiconductor layer, and
the third blocking layer fully covers the whole area of the second semiconductor layer in a top view of the substrate.

16. A display panel comprising:
a substrate comprising a display area and a sensor area, wherein the display area comprises a first pixel, and the sensor area comprises a second pixel, a wiring unit, and a transmission portion; and
a first blocking layer on the substrate,
wherein the second pixel comprises an organic light-emitting diode and a first semiconductor layer,
wherein the second pixel is electrically connected to the wiring unit,
wherein, the wiring unit and the first semiconductor layer are disposed above the first blocking layer,
wherein the wiring unit includes a plurality of wiring lines spaced apart from each other, and
wherein the first blocking layer covers at least a portion of the plurality of wiring lines and spaces spaced apart between the plurality of wiring lines in a cross sectional view.

17. The display panel of claim 16 , wherein a gate electrode is disposed on the first semiconductor layer, and
at least one wiring line of the plurality of wiring lines is arranged on a same layer as the gate electrode.

18. The display panel of claim 17 , wherein the at least one wiring line comprises at least one wiring line of a previous scan line, a scan line, an initialization voltage line or a light emission control line.

19. The display panel of claim 16 , wherein the plurality of wiring lines are spaced apart from each other in a direction horizontal to the substrate, and
a width of the first blocking layer is greater than a total width of the plurality of wiring lines.

20. The display panel of claim 16 , wherein the plurality of wiring lines are spaced apart from each other in a vertical direction of the substrate, and
the first blocking layer covers the plurality of wiring lines that are spaced apart from each other.

Assignees

• Samsung Display Co Ltd

Inventors

• Bae Injun
• Kim Chulho
• Park Yunhwan
• Jeon Jin
• Choi Beohmrock

Classifications

• H10K59/87 Primary

  Passivation; Containers; Encapsulations · CPC title

• H10K59/10

  OLED displays · CPC title

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title