Analog-to-digital converter and method for analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-12323158-B2
Application number	US-202217986471-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	Nov 23, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

An analog-to-digital converter is provided which is configured to output an n-bit signal in response to an analog input signal. n is greater than 1. The converter comprises n comparators, where each comparator is configured to output one bit of the n-bit signal and comprising a first input and a second input. A first comparator is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal. For the remaining comparators, an i-th comparator, i=2 . . . n, is configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device. The i-th input device is configured to selectively provide one of 2 i−1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

First claim

The invention claimed is:

1. An analog-to-digital converter configured to output an n-bit signal in response to an analog input signal, where n is greater than 1, the analog-to-digital converter comprising:
n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input,
wherein a first comparator is configured to receive a reference value at its first input and the analog input signal at its second input and to output the first, most significant bit of the n bit signal,
wherein for an i-th comparator, where i=2 . . . n, configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device configured to selectively provide one of 2 i−1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator such that the n-bit signal is a Gray code representation of the analog input signal.

2. The analog-to-digital converter of claim 1 , wherein each i-th input device, i=2 . . . n, is configured to be controlled by a logic combination of output signals of the first through (i−1)-th comparators.

3. The analog-to-digital converter of claim 2 , wherein the i-th input device is configured to switch the providing of the one of 2 i−1 reference values and the analog input signal between the first and second inputs of the i-th comparator based on an XOR combination of the output signals of the first through (i−1)-th comparators.

4. The analog-to-digital converter of claim 3 , wherein the input device of the i-th comparator, i=2 . . . n, comprises a switch device, which is configured to couple in a first position the first input of the i-th comparator to a first reference set and the second input of the i-th comparator to the analog input signal and to couple in a second position the second input of the i-th comparator to a second reference set and the first input of the i-th comparator to the analog input signal.

5. The analog-to-digital converter of claim 4 , wherein for the i-th comparator, i=2 . . . n, the first reference set is configured to provide one of first 2 i−2 reference values based on a logic combination of the outputs of the first through (i−2)-th comparators and wherein the second reference set is configured to provide one of second 2 i−2 reference values different from the first 2 i−2 reference values based on the logic combination.

6. The analog-to-digital converter of claim 1 , wherein for providing one of 2 i−1 reference values the analog-to-digital converter includes a digital-to-analog converter.

7. The analog-to-digital converter of claim 1 , wherein the analog-to-digital converter is configured to operate independently from a clock signal.

8. The analog-to-digital converter of claim 1 , further comprising a peak detection logic coupled to receive the n-bit signal and to determine a peak value of the n-bit signal over time.

9. The analog-to-digital converter of claim 8 , wherein the peak detection logic is configured to operate independently from a clock signal.

10. The analog-to-digital converter of claim 9 , wherein the peak detection logic, for each i-th bit, i=1-n, comprises an i-th latch configured to receive the 1-th bit, wherein the pe ak detection logic is configured such that of the n latches at most one latch, the k-th latch, is switched to transparent providing its input to its output at a given time, wherein the k-th latch is selected from the first to n-th latch with decreasing priority as the latch where for the first to k−1 latches the input corresponds to the output and for the k-th bit the decoded Gray code
indicates a higher value of the k-th bit than stored in the k-th latch when the peak detection logic is a maximum peak detection logic, or
indicates a lower value of the k-th bit than stored in the k-th latch when the peak detection logic is a minimum peak detection logic.

11. The analog-to-digital converter as in claim 1 , wherein the one of the 2 i−1 reference values is a first reference voltage; and
wherein the i-th input device is configured to switch between application of the first reference voltage to the first input of the i-th comparator and the second input of the i-th comparator.

12. The analog-to-digital converter as in claim 11 , wherein the i-th input device is configured to: i) during a first condition, apply the first reference voltage to the first input of the i-th comparator and apply the analog input signal to the second input of the i-th comparator, and ii) during a second condition, apply the first reference voltage to the second input of the i-th comparator and apply the analog input signal to the first input of the i-th comparator.

13. The analog-to-digital converter as in claim 1 , wherein the i-th input device is configured to: i) during a first condition, apply a first reference voltage to the first input of the i-th comparator and apply the analog input signal to the second input of the i-th comparator, and ii) a during a second condition, apply a second reference voltage to the second input of the i-th comparator and apply the analog input signal to the first input of the i-th comparator.

14. The analog-to-digital converter as in claim 1 , wherein for i=2, the i-th comparator is a second comparator of the n comparators, the second comparator including an inverting input node and a non-inverting input node;
wherein for i=2, the i-th bit is a second bit of the n bit signal;
wherein for i=2, the i-th input device is a second input device of the analog-to-digital converter;
wherein the second input device includes switch circuitry operative to switch between: i) input of the analog input signal to the inverting input node of the second comparator, and ii) input of the analog input signal to the non-inverting input node of the second comparator.

15. The analog-to-digital converter as in claim 14 , wherein the switch circuitry is operative to, during a first condition: i) apply the analog input signal to the non-inverting input node of the second comparator, and ii) apply a first reference voltage to the inverting input node of the second comparator; and
wherein the switch circuitry is operative to, during a second condition: i) apply the analog input signal to the inverting input node of the second comparator, and ii) apply a second reference voltage to the non-inverting input node of the second comparator.

16. An analog-to-digital conversion method for outputting an n-bit signal in response to an analog input signal, where n is greater than 1, the analog-to-digital conversion method comprising:
n comparators ( 11 ), each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input,
providing a reference value to a first input of a first comparator and the analog input signal to a second input of the first comparator, and obtaining the 1 st , most significant bit of the n bit signal, at the output of the first comparator, and, for each i-th bit, where i=2 . . . n:
selectively providing one of 2 i−1 reference values to one of the first or second input of a respective i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, and obtaining the i-th bit of the n bit signal at the output of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

17. The method of claim 16 , wherein the selectively providing for the i-th bit is based on a

Assignees

• Infineon Technologies Austria Ag

Inventors

• Feldtkeller Martin

Classifications

• H03M1/285

  of the unit Hamming distance type, e.g. Gray code · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/368 Primary

  having a single comparator per bit, e.g. of the folding type · CPC title

• H03M1/42 Primary

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title