Operational transconductance amplifier circuit including active inductor

Patent metadata

Field	Value
Publication number	US-12323115-B2
Application number	US-202117536064-A
Country	US
Kind code	B2
Filing date	Nov 28, 2021
Priority date	Dec 29, 2020
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.

First claim

What is claimed is:

1. An operational transconductance amplifier comprising:
an input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals;
a first current mirror circuit configured to generate a first mirror current based on the first differential current and output the first mirror current via a first output terminal; and
a second current mirror circuit configured to generate a second mirror current based on the second differential current and output the second mirror current via a first node of a third current mirror circuit,
wherein the second current mirror circuit and the third current mirror circuit are connected to each other through the first node,
wherein the third current mirror circuit is configured to generate a third mirror current based on the second mirror current and output the third mirror current via the first output terminal,
wherein the first current mirror circuit and the second current mirror circuit respectively comprise a first active inductor and a second active inductor each including a P-channel transistor, a capacitor, and a resistor connected to each other, and
wherein the third current mirror circuit comprises a third active inductor including an N-channel transistor, a capacitor and a resistor connected to each other.

2. The operational transconductance amplifier of claim 1 , wherein the input circuit includes a first input stage and a second input stage, and the operational transconductance amplifier further comprising:
a feedback circuit configured to electrically connect the first current mirror circuit to the second current mirror circuit and amplify gains of the first input stage and the second input stage.

3. The operational transconductance amplifier of claim 1 , further comprising:
a fourth current mirror circuit configured to generate a fifth mirror current based on a fourth mirror current, and output the fifth mirror current via a second output terminal,
wherein the fourth mirror current is generated by the first current mirror circuit based on the first differential current, and
wherein the fourth current mirror circuit is connected to the second output terminal and comprises a fourth active inductor including an N-channel transistor, a capacitor, and a resistor connected to each other.

4. The operational transconductance amplifier of claim 3 , wherein the second current mirror circuit is configured to further generate a sixth mirror current based on the second differential current and output the sixth mirror current via the second output terminal.

5. The operational transconductance amplifier of claim 4 , wherein the operational transconductance amplifier is configured to output an output signal via the first output terminal based on a difference between the first mirror current and the third mirror current.

6. The operational transconductance amplifier of claim 4 , wherein the operational transconductance amplifier is configured to output an output signal via the second output terminal based on a difference between the fifth mirror current and the sixth mirror current.

7. The operational transconductance amplifier of claim 6 , wherein each of the first mirror current and the sixth mirror current corresponds to a current generated through current mirroring once, and
wherein each of the third mirror current and the fifth mirror current corresponds to a current generated through current mirroring twice.

8. The operational transconductance amplifier of claim 7 , wherein the operational transconductance amplifier is configured such that:
a duty cycle of the first mirror current matches a duty cycle of the third mirror current, and
a duty cycle of the sixth mirror current matches a duty cycle of the fifth mirror current.

9. The operational transconductance amplifier of claim 4 , wherein the first current mirror circuit further comprises a first P-channel transistor configured to generate the first mirror current and a second P-channel transistor configured to generate the fourth mirror current,
wherein the first P-channel transistor is electrically connected to the first output terminal, and
wherein the second P-channel transistor forms a common drain node with the fourth active inductor of the fourth current mirror circuit.

10. The operational transconductance amplifier of claim 4 , wherein the second current mirror circuit further comprises a third P-channel transistor configured to generate the second mirror current and a fourth P-channel transistor configured to generate the sixth mirror current,
wherein the fourth P-channel transistor is electrically connected to the second output terminal, and
wherein the third P-channel transistor forms a common drain node with the third active inductor of the third current mirror circuit.

11. A memory device comprising:
a memory cell array including multiple memory blocks that each include a plurality of memory cells connected to word lines and bit lines arranged in rows and columns, and configured to perform a write operation and a read operation for the plurality of memory cells by using an internal power supply voltage; and
a clock buffer configured to receive a pair of differential input signals having a clock signal and an inverted clock signal and correct a duty cycle of the clock signal,
wherein the clock buffer comprises:
an input circuit configured to generate a first differential current and a second differential current based on the clock signal and the inverted clock signal;
a first current mirror circuit including a first active inductor including a P-channel transistor and configured to generate a first mirror current and a second mirror current based on the first differential current;
a second current mirror circuit including a second active inductor including a P-channel transistor and configured to generate a third mirror current and a fourth mirror current based on the second differential current;
a third current mirror circuit including a third active inductor including an N-channel transistor and configured to generate a fifth mirror current based on the third mirror current; and
a fourth current mirror circuit including a fourth active inductor including an N-channel transistor and configured to generate a sixth mirror current based on the second mirror current.

12. The memory device of claim 11 , wherein the first current mirror circuit is configured to output the first mirror current via a first output terminal of the clock buffer, and output the second mirror current as a reference current via a first node of the fourth active inductor of the fourth current mirror circuit,
wherein the first current mirror circuit and the fourth current mirror circuit are connected to each other through the first node,
wherein the second current mirror circuit is configured to output the third mirror current as the reference current via a second node of the third active inductor of the third current mirror circuit,
wherein the second current mirror circuit and the third current mirror circuit are connected to each other through the second node, and
wherein the fourth current mirror circuit is configured to output the fourth mirror current via a second output terminal of the clock buffer.

13. The memory device of claim 12 , wherein the clock buffer is configured to output an output signal via the first output terminal based on a difference between the first mirror current and the fifth mirror current.

14. The memory device of claim 13 , wherein the clock buffer is configured to output an inverted output signal via the second outpu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Baekjin
• Cho Youngchul
• Park Seungjin
• Choi Youngdon
• Choi Junghwan

Classifications

• H03F2200/153

  Feedback used to stabilise the amplifier · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03F2200/36

  the amplifier comprising means for increasing the bandwidth · CPC title

• H03F2200/84

  A cross coupling circuit being realized by current mirrors · CPC title