Substrate integrated with passive devices and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12322669-B2
Application number	US-202117772272-A
Country	US
Kind code	B2
Filing date	Apr 23, 2021
Priority date	Apr 23, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A substrate integrated with passive devices and a manufacturing method thereof are provided. The manufacturing method of the substrate integrated with passive devices includes: providing a transparent dielectric layer with first connection vias therein, wherein the transparent dielectric layer includes a first surface and a second surface, which are opposite to each other along a thickness direction of the transparent dielectric layer; integrating the passive devices onto the transparent dielectric layer, wherein the passive devices include at least an inductor, the integrating the passive devices onto the transparent dielectric layer includes: forming first sub-structures on the first surface of the transparent dielectric layer, forming second sub-structures on the second surface, and forming first connection electrodes in the first connection vias, respectively; wherein the first sub-structures, the first connection electrodes and the second sub-structures are connected together to form a coil structure of the inductor.

First claim

What is claimed is:

1. A manufacturing method of a substrate integrated with passive devices, comprising:
providing a transparent dielectric layer with first connection vias therein, wherein the transparent dielectric layer comprises a first surface and a second surface, which are opposite to each other along a thickness direction of the transparent dielectric layer;
integrating the passive devices onto the transparent dielectric layer, wherein the passive devices comprise at least an inductor,
wherein the integrating the passive devices onto the transparent dielectric layer comprises:
forming first sub-structures on the first surface of the transparent dielectric layer, forming second sub-structures on the second surface, and forming first connection electrodes in the first connection vias, respectively; wherein the first sub-structures, the first connection electrodes and the second sub-structures are connected together to form a coil structure of the inductor; and
the manufacturing method further comprises:
sequentially forming a second protective layer and a second planarization layer on a side of the first sub-structures distal to the transparent dielectric layer.

2. The manufacturing method according to claim 1 , wherein
providing the transparent dielectric layer comprises processing the transparent dielectric layer to form the first connection vias penetrating through the transparent dielectric layer in the thickness direction of the transparent dielectric layer;
forming the first connection electrodes in the first connection vias comprises making the first connection electrodes at least cover inner walls of the first connection vias;
forming a pattern comprising the second sub-structures on the second surface through a patterning process; and
forming a pattern of the first sub-structures on the first surface through a patterning process.

3. The manufacturing method according to claim 2 , wherein, prior to the forming the first connection electrodes in the first connection vias, the manufacturing method further comprises:
attaching the first surface of the transparent dielectric layer to a first substrate;
the manufacturing method further comprises:
prior to forming the first sub-structures, peeling off the first substrate from the first surface of the transparent dielectric layer; and attaching a second substrate to a side of the second sub-structures away from the transparent dielectric layer.

4. The manufacturing method according to claim 1 , wherein forming the first connection vias is subsequent to the forming the second sub-structures.

5. The manufacturing method according to claim 4 , wherein the forming the first connection vias comprises:
thinning the transparent dielectric layer, and processing the transparent dielectric layer to form the first connection vias penetrating through the transparent dielectric layer in the thickness direction of the transparent dielectric layer.

6. The manufacturing method according to claim 1 , wherein the passive devices further comprises a capacitor; the manufacturing method further comprises:
forming a pattern comprising a first plate of the capacitor on the second surface through a patterning process;
forming a first interlayer dielectric layer on a side of the first plate of the capacitor distal to the transparent dielectric layer;
forming a pattern comprising a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer, through a patterning process.

7. A manufacturing method of a substrate integrated with passive devices, comprising:
providing a transparent dielectric layer with first connection vias therein, wherein the transparent dielectric layer comprises a first surface and a second surface, which are opposite to each other along a thickness direction of the transparent dielectric layer;
integrating the passive devices onto the transparent dielectric layer, wherein the passive devices comprise at least an inductor,
wherein the integrating the passive devices onto the transparent dielectric layer comprises:
forming first sub-structures on the first surface of the transparent dielectric layer, forming second sub-structures on the second surface, and forming first connection electrodes in the first connection vias, respectively; wherein the first sub-structures, the first connection electrodes and the second sub-structures are connected together to form a coil structure of the inductor;
wherein the passive devices further comprises a capacitor; the manufacturing method further comprises:
forming a pattern comprising a first plate of the capacitor on the second surface through a patterning process;
forming a first interlayer dielectric layer on a side of the first plate of the capacitor distal to the transparent dielectric layer; and
forming a pattern comprising a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer, through a patterning process;
wherein the second sub-structures comprise a first conductive film layer and a second conductive film layer sequentially arranged along a direction away from the second surface;
the first conductive film layer and the first plate of the capacitor are manufactured through one patterning process;
the manufacturing method further comprises:
forming a second interlayer dielectric layer on a side of the second plate of the capacitor distal to the transparent dielectric layer, and forming a second connection via penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer;
wherein the second conductive film layer is formed on a side of the second interlayer dielectric layer distal to the transparent dielectric layer, and is connected to the first conductive film layer through the second connection via.

8. The manufacturing method according to claim 7 , further comprising: grinding the first conductive film layer and the first plate of the capacitor.

9. The manufacturing method according to claim 7 , further comprising:
forming a third connection via penetrating through the second interlayer dielectric layer while forming the second connection via; forming a second connection electrode while forming the second conductive film layer, wherein the second connection electrode is connected to the second plate of the capacitor through the third connection via;
sequentially depositing a first protective layer and a first planarization layer on a side of the second conductive film layer and the second connection electrode distal to the second interlayer dielectric layer;
forming a fourth connection via and a fifth connection via penetrating through the first protective layer and the first planarization layer; and
forming a first connection pad and a second connection pad; wherein the first connection pad is connected to a lead terminal of the inductor through the four connection via, and the second connection pad is connected to the second connection electrode through the fifth connection pad.

10. The manufacturing method according to claim 1 , wherein in a case where the first connection electrodes do not fully fill the first connection vias, respectively, forming filling structures in the first connection vias, respectively, between the forming the first connection electrodes and the forming the second sub-structures.

11. The manufacturing method according to claim 1 , wherein the transparent dielectric layer comprises a glass substrate.

12. A substrate integrated with passive devices, comprising a transparent dielectric layer and the passive devices integrated on the transparent

Assignees

• Beijing Boe Sensor Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Che Chuncheng
• Liu Feng
• Xiao Yuelei
• Li Yue
• Du Guochen
• Cao Xue
• Wu Yifan
• Chang Wenbo

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/692 Primary

  Ceramics or glasses · CPC title

• H10D1/60

  Capacitors · CPC title