Digital verify failbit count (VFC) circuit

Patent metadata

Field	Value
Publication number	US-12322465-B2
Application number	US-202318149842-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Dec 26, 2022
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A failbit counting method includes sequentially receiving, at an input of a counter, a bit group including one or more verification bits. Each of the one or more verification bits is a fail bit or a pass bit. The counter includes one or more counter stages coupled in series from the input. The method further includes, for one verification bit of the one or more verification bits, performing a determination process according to a position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including one or more memory sections each including one or more memory cells;
a buffer circuit including one or more buffers each coupled to one of the one or more memory sections;
a verify failbit count (VFC) circuit coupled to the buffer circuit and including a counter, the counter including one or more counter stages coupled in series from an input of the counter; and
a control logic coupled to the VFC circuit and configured to control the counter to:
sequentially receive, at the input of the counter, a bit group including one or more verification bits, each of the one or more verification bits indicating a verification result of one memory cell in the memory cell array and being a fail bit or a pass bit; and
for one verification bit of the one or more verification bits, perform a determination process according to a position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.

2. A failbit counting method for the memory device of claim 1 , comprising:
sequentially receiving, at the input of the counter, the bit group including the one or more verification bits; and
for one verification bit of the one or more verification bits, performing the determination process according to the position of the one verification bit in the group to select one of the one or more counter stages for writing a fail bit or to decide to discard the one verification bit.

3. The failbit counting method according to claim 2 , wherein performing the determination process according to the position of the one verification bit in the group includes, in response to the one verification bit being a pass bit, deciding to discard the one verification bit.

4. The failbit counting method according to claim 2 , wherein performing the determination process according to the position of the one verification bit in the group includes:
in response to the one verification bit being a fail bit, selecting a closest available counter stage for writing a fail bit, the closest available counter stage being one of the one or more counter stages that does not have a fail bit already stored therein and is closest to the input of the counter.

5. The failbit counting method according to claim 2 , wherein performing the determination process according to the position of the one verification bit in the group includes:
in response to the one verification bit being a first verification bit in the bit group, determining whether the one verification bit is a fail bit.

6. The failbit counting method according to claim 5 , wherein performing the determination process according to the position of the one verification bit in the group further includes:
in response to the one verification bit being a fail bit, selecting a first counter stage of the one or more counter stages for writing a fail bit.

7. The failbit counting method according to claim 2 , wherein:
the one or more counter stages include a plurality of counter stages; and
performing the determination process according to the position of the one verification bit in the group includes:
in response to the verification bit being an N-th verification bit in the bit group, determining whether a condition that the one verification bit is a fail bit and a first counter stage to an (N−1)-th counter stage of the plurality of counter stages each already have a fail bit stored therein is satisfied, N being an integer greater than one.

8. The failbit counting method according to claim 7 , wherein performing the determination process according to the position of the one verification bit in the group further includes:
in response to the condition being satisfied, selecting an N-th counter stage of the plurality of counter stages for writing a fail bit.

9. The failbit counting method according to claim 7 , wherein:
the plurality of counter stages include three or more counter stages, N is an integer greater than two, and the condition is a first condition; and
performing the determination process according to the position of the one verification bit in the group further includes:
in response to the first condition being not satisfied, determining whether a second condition that the one verification bit is a fail bit and the first counter stage to an (N−2)-th counter stage of the plurality of counter stages each already have a fail bit stored therein is satisfied.

10. The failbit counting method according to claim 9 , wherein performing the determination process according to the position of the one verification bit in the group further includes:
in response to the second condition being satisfied, selecting the (N−1)-th counter stage for writing a fail bit.

11. The memory device according to claim 1 , wherein the control logic is further configured to control the counter to, in response to the one verification bit being a pass bit, decide to discard the one verification bit.

12. The memory device according to claim 1 , wherein the control logic is further configured to control the counter to:
in response to the one verification bit being a fail bit, select a closest available counter stage for writing a fail bit, the closest available counter stage being one of the one or more counter stages that does not have a fail bit already stored therein and is closest to the input of the counter.

13. The memory device according to claim 1 , wherein the control logic is further configured to control the counter to:
in response to the one verification bit being a first verification bit in the bit group, determine whether the one verification bit is a fail bit.

14. The memory device according to claim 13 , wherein the control logic is further configured to control the counter to:
in response to the one verification bit being a fail bit, select a first counter stage of the one or more counter stages for writing a fail bit.

15. The memory device according to claim 1 , wherein:
the one or more counter stages include a plurality of counter stages; and
the control logic is further configured to control the counter to:
in response to the verification bit being an N-th verification bit in the bit group, determine whether a condition that the one verification bit is a fail bit and a first counter stage to an (N−1)-th counter stage of the plurality of counter stages each already have a fail bit stored therein is satisfied, N being an integer greater than one.

16. The memory device according to claim 15 , wherein the control logic is further configured to control the counter to:
in response to the condition being satisfied, select an N-th counter stage of the plurality of counter stages for writing a fail bit.

17. The memory device according to claim 15 , wherein:
the plurality of counter stages include three or more counter stages, N is an integer greater than two, and the condition is a first condition; and
the control logic is further configured to control the counter to:
in response to the first condition being not satisfied, determine whether a second condition that the one verification bit is a fail bit and the first counter stage to an (N−2)-th counter stage of the plurality of counter stages each already have a fail bit stored therein is satisfied.

18. The memory device according to claim 17 , wherein the control logic is further configured to control the counter to:
in response to the second condition being satisfied, select the (N−1)-th counter stage for wr

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Teng
• Kuriyama Masao

Classifications

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/56012

  Timing aspects, clock generation, synchronisation · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C29/70 Primary

  Masking faults in memories by using spares or by reconfiguring · CPC title