Apparatus for optical fiber-to-photonic chip connection and associated methods

Patent metadata

Field	Value
Publication number	US-12321022-B2
Application number	US-202016866528-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Feb 23, 2017
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A photonic chip includes a substrate, an electrical isolation region formed over the substrate, and a front end of line (FEOL) region formed over the electrical isolation region. The photonic chip also includes an optical coupling region. The electrical isolation region and the FEOL region and a portion of the substrate are removed within the optical coupling region. A top surface of a the substrate within the optical coupling region includes a plurality of grooves configured to receive and align a plurality of optical fibers. The grooves are formed at a vertical depth within the substrate to provide for alignment of optical cores of the plurality of optical fibers with the FEOL region when the plurality of optical fibers are positioned within the plurality of grooves within the optical coupling region.

First claim

What is claimed is:

1. A photonic chip, comprising:
a substrate;
a front end of line region formed over the substrate, the front end of line region including transistors and electro-optic devices; and
an optical coupling region formed to receive a plurality of optical fibers, wherein the front end of line region is removed within the optical coupling region, wherein the optical coupling region provides for alignment of optical cores of the plurality of optical fibers with the front end of line region when the plurality of optical fibers are positioned within the optical coupling region.

2. The photonic chip as recited in claim 1 , further comprising:
a buried oxide region disposed between the substrate and the front end of line region.

3. The photonic chip as recited in claim 2 , wherein the buried oxide region is removed within the optical coupling region.

4. The photonic chip as recited in claim 1 , further comprising:
a shallow trench isolation region disposed between the substrate and the front end of line region.

5. The photonic chip as recited in claim 4 , wherein the shallow trench isolation region is removed within the optical coupling region.

6. The photonic chip as recited in claim 1 , further comprising:
a deep trench isolation region disposed between the substrate and the front end of line region.

7. The photonic chip as recited in claim 6 , wherein the deep trench isolation region is removed within the optical coupling region.

8. The photonic chip as recited in claim 1 , wherein the optical coupling region includes alignment structures for aligning the optical cores of the plurality of optical fibers with the front end of line region.

9. The photonic chip as recited in claim 1 , wherein the alignment structures include a plurality of recessed regions that extend across the optical coupling region in a substantially parallel manner.

10. The photonic chip as recited in claim 1 , wherein the optical coupling region provides for alignment of optical cores of the plurality of optical fibers with a respective plurality of optical waveguides within the front end of line region.

11. The photonic chip as recited in claim 1 , wherein the optical coupling region provides for alignment of optical cores of the plurality of optical fibers with a respective plurality of optical grating couplers within the front end of line region.

12. The photonic chip as recited in claim 1 , further comprising:
a back end of line region formed over the front end of line region, the back end of line region removed within the optical coupling region, the back end of line region including metal interconnect structures.

13. The photonic chip as recited in claim 1 , further comprising:
an optical isolating material disposed between the substrate and the front end of line region.

14. A photonic chip, comprising:
a substrate, wherein a portion of the substrate is removed to form an optical coupling region, the optical coupling region formed to receive a plurality of optical fibers; and
a front end of line region formed over the substrate, the front end of line region including transistors and electro-optic devices, the front end of line region including a plurality of optical grating couplers positioned to optically couple with respective optical cores of the plurality of optical fibers through a corresponding optical turning mechanism.

15. The photonic chip as recited in claim 14 , wherein the substrate at an edge of the optical coupling region provides a stop barrier for the plurality of optical fibers.

16. The photonic chip as recited in claim 14 , further comprising:
an electrical isolation region disposed between the substrate and the front end of line region, wherein openings exist in the electrical isolation region to enable light transmission between the plurality of optical grating couplers and the plurality of optical fibers.

17. The photonic chip as recited in claim 16 , wherein the electrical isolation region is either one or more of a buried oxide region, a shallow trench isolation region, and a deep trench isolation region.

18. The photonic chip as recited in claim 14 , wherein the optical coupling region includes alignment structures for aligning the optical cores of the plurality of optical fibers as needed to optically couple the optical grating couplers with respective optical cores of the plurality of optical fibers through the corresponding optical turning mechanism.

19. The photonic chip as recited in claim 14 , wherein a depth of the portion of the substrate that is removed to form the optical coupling region is greater than an outer diameter of any of the plurality of optical fibers, wherein the depth of the portion of the substrate that is removed to form the optical coupling region is measured perpendicular to a bottom surface of the substrate.

20. The photonic chip as recited in claim 14 , further comprising:
a back end of line region formed over the front end of line region, the back end of line region including metal interconnect structures.

Assignees

• Ayar Labs Inc

Inventors

• Wade Mark
• Sun Chen
• Fini john
• Meade Roy Edward
• Stojanovic Vladimir
• Wright Alexandra

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• G02B6/4214

  the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence) · CPC title

• G02B6/3636

  the mechanical coupling means being grooves (G02B6/3652 takes precedence) · CPC title

• G02B6/4283

  with electrical insulation means · CPC title

• G02B6/4239

  Adhesive bonding; Encapsulation with polymer material · CPC title