Technologies for memory and I/O efficient operations on homomorphically encrypted data

Patent metadata

Field	Value
Publication number	US-12316735-B2
Application number	US-202017133711-A
Country	US
Kind code	B2
Filing date	Dec 24, 2020
Priority date	Dec 24, 2020
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

First claim

The invention claimed is:

1. A homomorphic encryption processor comprising:
a memory to store one or more ciphertext blocks;
one or more compute engines communicatively coupled to the memory; and
shapeshifter circuitry to:
create an operand for a first compute operation on the one or more compute engines, wherein to create the operand comprises to create an operand ciphertext block based on the one or more ciphertext blocks in parallel with performance of a second compute operation on the one or more compute engines, wherein to create the operand comprises to apply a mask to one of the one or more ciphertext blocks to create a masked ciphertext block; and
send the operand to the one or more compute engines,

wherein the one or more compute engines are to perform the first operation with use of the operand.

2. The homomorphic encryption processor of claim 1 , wherein to create the operand further comprises to perform a rotate operation on the masked ciphertext block.

3. The homomorphic encryption processor of claim 1 , wherein the shapeshifter circuitry is to receive an instruction from the one or more compute engines to create the operand, wherein the instruction indicates which slot values of the one or more ciphertext blocks should be in which slots of the operand.

4. The homomorphic encryption processor of claim 1 , wherein the shapeshifter circuitry is further to create a second operand based on a temporal or spatial locality of data in a second operand of the current compute operation.

5. A compute device for performance of operations on homomorphically encrypted data, the compute device comprising:
a processor;
a memory communicatively coupled to the processor; and
one or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed by the compute device, cause the compute device to:
receive, from a remote compute device, one or more ciphertext blocks, wherein each of the one or more ciphertext blocks is homomorphically encrypted, wherein each of the one or more ciphertext blocks includes a plurality of ciphertext slot values;
create a first operand with use of a first ciphertext slot value of the plurality of ciphertext slot values of a first ciphertext block of the one or more ciphertext blocks;
create a second operand with use of a second ciphertext slot value of the plurality of ciphertext slot values of the first ciphertext block of the one or more ciphertext blocks, wherein the first operand is different from the second operand and wherein the second ciphertext slot value is different from the first ciphertext slot value;
perform a first operation on homomorphically encrypted data with use of the first operand; and
perform a second operation on homomorphically encrypted data with use of the second operand; and

a homomorphic encryption processor comprising:
cache memory to store one or more ciphertext blocks;
one or more compute engines communicatively coupled to the cache memory; and
shapeshifter circuitry,
wherein the plurality of instructions causes the shapeshifter circuitry to create the first operand and create the second operand,
wherein the plurality of instructions causes the one or more compute engines to perform the first operation and perform the second operation, wherein the plurality of instructions are to cause the shapeshifter circuitry to create the first operand by applying a mask to one of the one or more ciphertext blocks to create a masked ciphertext block.

6. The compute device of claim 5 , wherein to create the first operand comprises to create the second operand in parallel with performance of the first operation.

7. The compute device of claim 5 , wherein to create the first operand with use of the first ciphertext slot value comprises to copy the first ciphertext slot value to each slot value of the operand ciphertext block.

8. The compute device of claim 7 , wherein the first ciphertext block comprises a plurality of filters of a convolutional neural network, wherein a second ciphertext block of the one or more ciphertext blocks comprises pixels of a channel of an image to be processed by the compute device,
wherein to copy the first ciphertext slot value to each slot value of the operand ciphertext block comprises to copy a filter of the plurality of filters to each slot value of the operand ciphertext block,
wherein to perform the first operation comprises to apply the filter to the pixels of the channel of the image to be processed.

9. The compute device of claim 5 , wherein each of the one or more ciphertext blocks is encrypted based on a lattice-based cryptographic scheme.

10. The compute device of claim 9 , wherein the lattice-based cryptographic scheme is based on ring learning with errors.

11. A compute device for performance of operations on homomorphically encrypted data, the compute device comprising:
a processor;
a memory communicatively coupled to the processor; and
one or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed by the compute device, cause the compute device to:
determine a plurality of workload parameters for a workload;
pack the plurality of workload parameters into one plaintext block, wherein the plurality of workload parameters are to be used in different operands during execution of the workload;
encrypt the plaintext block to a ciphertext block with use of a homomorphic encryption algorithm;
send the encrypted ciphertext block to a remote compute device for execution of the workload; and
encrypt pixels of a channel of an image to be processed by the remote compute device to a second ciphertext block, wherein the plurality of workload parameters packed into the one ciphertext block comprise a plurality of filters of a convolutional neural network, wherein each filter of the plurality of filters is to be applied to all pixels of the channel of the image to be processed.

Assignees

• Intel Corp

Inventors

• Suresh Vikram B
• Cammarota Rosario
• Mathew Sanu K
• Chishti Zeshan A
• Kumar Raghavan
• Misoczki Rafael

Classifications

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06N20/00

  Machine learning · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06F7/552

  Powers or roots {, e.g. Pythagorean sums} · CPC title