Continuous-time delta-sigma analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12316340-B2
Application number	US-202318157409-A
Country	US
Kind code	B2
Filing date	Jan 20, 2023
Priority date	Jan 20, 2023
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes an ADC with a continuous time integrator. The continuous time integrator includes an amplifier having an amplifier input and an amplifier output, a capacitor coupled between the amplifier input and the amplifier output, and a resistor. The resistor provides a first current for an integration in response to an analog input. The ADC also includes a DAC configured to generate a second current at an DAC output based on a digital output of the ADC and includes a switch circuit with a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input. The switch circuit is configured to couple the DAC output with the amplifier input for a summation of the second current with the first current for the integration based on an integration control signal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an analog-to-digital converter (ADC) comprising:
a continuous-time integrator including:
an amplifier having an amplifier input and an amplifier output,
a capacitor coupled between the amplifier input and the amplifier output, and
a resistor with a first resistor terminal configured to receive an analog input and a second resistor terminal coupled to the amplifier input, the resistor configured to provide a first current for an integration in response to the analog input;

a digital-to-analog converter (DAC) configured to generate a second current at a DAC output based on a digital output of the ADC; and
a switch module comprising:
multiple configurable switch circuits responsive to one or more configuration control signals, with a configuration of the multiple configurable switch circuits providing a summing node; and
a switch circuit having a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input, with the switch circuit configured to couple the DAC output with the amplifier input for a summation, at the summing node, of the second current with the first current for the integration based on an integration control signal.

2. The integrated circuit of claim 1 , further comprising:
an integration control generator configured to generate the integration control signal based on a mode of the DAC.

3. The integrated circuit of claim 2 , wherein in a first mode of the DAC:
the integration control generator is configured to generate the integration control signal as a clock signal with a constant on time in a clock period, the constant on time corresponding to an integration time for the continuous-time integrator.

4. The integrated circuit of claim 3 , wherein the integration control generator comprises:
a timing control loop circuit configured to generate the clock signal with the constant on time set based on a resistor-capacitor time constant.

5. The integrated circuit of claim 3 , wherein in a second mode of the DAC:
the integration control generator is configured to generate the integration control signal with a constant non-zero voltage level.

6. The integrated circuit of claim 5 , further comprising:
a first configuration switch of the multiple configurable switch circuits configured to couple the second resistor terminal with the amplifier input in the first mode and the second mode of the DAC; and
a second configuration switch of the multiple configurable switch circuits configured to decouple the second resistor terminal from the first switch circuit terminal of the switch circuit in the first mode and the second mode of the DAC.

7. The integrated circuit of claim 6 , wherein:
the first configuration switch is configured to decouple the second resistor terminal from the amplifier input in a third mode of the DAC; and
the second configuration switch is configured to couple the second resistor terminal with the first switch circuit terminal of the switch circuit in the third mode of the DAC.

8. The integrated circuit of claim 7 , wherein in the third mode of the DAC:
the integration control generator is configured to generate the integration control signal as a clock signal with an adjustable on time of a non-zero voltage level in a clock period, the adjustable on time corresponding to an adjustable integration time for the continuous-time integrator.

9. The integrated circuit of claim 7 , further comprising:
a configuration circuit configured to generate the one or more configuration control signals to control the first configuration switch and the second configuration switch in response to a selected mode from the group of the first mode, the second mode, and the third mode of the DAC.

10. A method of operating an analog-to-digital converter (ADC), comprising:
providing, by a resistor, a first current in response to an analog input;
generating, by a digital-to-analog converter (DAC), a second current in response to a digital output of the ADC;
configuring, using one or more configuration control signals, multiple configurable switch circuits to provide a summing node;
controlling a switch circuit based on an integration control signal to transmit the second current to the summing node;
combining the first current and the second current at the summing node to generate an integration current;
integrating the integration current over a capacitor to generate an integration output; and
adjusting the digital output based on the integration output.

11. The method of claim 10 , further comprising:
generating the integration control signal based on a mode of the DAC.

12. The method of claim 11 , wherein in a first mode of the DAC, the method further comprises:
generating the integration control signal as a clock signal with a constant on time in a clock period, the constant on time corresponding to an integration time.

13. The method of claim 12 , wherein in a second mode of the DAC, the method further comprises:
generating the integration control signal with a constant non-zero voltage level.

14. The method of claim 13 , further comprising:
coupling the resistor with the capacitor in the first mode and the second mode of the DAC; and
decoupling the resistor from the switch circuit in the first mode and the second mode of the DAC.

15. The method of claim 14 , further comprising:
decoupling the resistor from the capacitor in a third mode of the DAC; and
coupling the resistor with the switch circuit in the third mode of the DAC.

16. The method of claim 15 , wherein in the third mode of the DAC, the method further comprises:
generating the integration control signal as a clock signal with an adjustable on time of a non-zero voltage level in a clock period, the adjustable on time corresponding to an adjustable integration time.

17. The method of claim 15 , further comprising:
generating one or more configuration control signals in response to a selected mode from the group of the first mode, the second mode, and the third mode of the DAC.

18. A method of using an analog-to-digital converter (ADC), comprising:
storing a selected mode of a digital-to-analog converter (DAC) in the ADC;
generating one or more configuration control signals based on the selected mode of the DAC;
generating an integration control signal based on the selected mode of the DAC;
configuring, based on the one or more configuration control signals, one of a first terminal of a switch circuit or a second terminal of the switch circuit as a summing node to combine a first current and a second current, the first current being generated in response to an analog input and the second current being generated by the DAC in response to a digital output of the ADC, with the first terminal of the switch circuit being coupled with an output terminal of the DAC and the second terminal of the switch circuit being coupled with a capacitor for integration; and
controlling the switch circuit based on the integration control signal, wherein a combined current resulting from combining the first current and the second current is provided to the capacitor to generate an integration output and the digital output of the ADC is adjusted based on the integration output.

19. The method of claim 18 , wherein the selected mode is a first mode, the method further comprising:
generating the one or more configuration control signals that configure the second terminal of the switch circuit as the summing nod

Assignees

• Analog Devices Inc

Inventors

• Canniff Daniel
• Markova Mariana Tosheva

Classifications

• H03M1/70

  Automatic control for modifying converter range · CPC title

• H03M3/372

  Jitter reduction · CPC title

• H03M1/50 Primary

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title