Method for operating a converter, converter and computer program product

Patent metadata

Field	Value
Publication number	US-12316236-B2
Application number	US-202118280115-A
Country	US
Kind code	B2
Filing date	Mar 4, 2021
Priority date	Mar 4, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A method is configured for operating a converter ( 10 ) which is implemented as a modular-multilevel converter and comprises a control arrangement ( 38 ) and a number M of phase-legs ( 21 to 29 ). The method comprises detecting whether the converter ( 10 ) has to be set into one mode of a group comprising a static synchronous compensator mode or a grid unbalance mode, generating mode control signals (MCS) depending on the detected mode, generating balance voltage reference signals (u bal,ref ) depending on a first side frequency (ω g ), a second side frequency (ωm), second side current reference signals (im,ref) and the mode control signals (MCS), generating a phase-leg control signal (u ref ), generating cell control signals ( 51 to S 4 ) and providing the cell control signals ( 51 to S 4 ) to semiconductor switches ( 41 to 44 ) of cells ( 31 ) of the phase-legs ( 21 to 29 ).

First claim

The invention claimed is:

1. A method for operating a converter,
wherein the converter is implemented as a modular-multilevel converter and comprises
a control arrangement and
a first side, a second side and a number M of phase-legs which are arranged between the first side and the second side, wherein each of the number M of phase-legs comprises at least a cell with a capacitor and semiconductor switches,

wherein the converter is realized as a direct AC/AC converter, and
wherein each of the number M of phase-legs comprises a number N of cells which are realized as full bridge cells,
the method comprising:
detecting whether the converter has to be set into one mode of a group comprising:
a static synchronous compensator mode in case a voltage of at least one terminal on the first side of the converter has constantly zero Volt and/or a machine coupled to the second side of the converter has a standstill, or
a grid unbalance mode,
generating mode control signals (MCS) depending on the detected mode,
generating balance voltage reference signals (u bal,ref ) depending on a first side frequency (ω g ), a second side frequency (ω m ), second side current reference signals (i m,ref ), measured phase-leg capacitor signals (u CΣ,yxn ) and the mode control signals (MCS) by the control arrangement,
generating a phase-leg control signal (u ref ) for each of the number M of phase-legs depending on first side voltage reference signals (u g,conv,ref ), second side voltage reference signals (u m,conv,ref ) and the balance voltage reference signals (u bal,ref ) by a reference generator of the control arrangement,
generating cell control signals by a modulator of the control arrangement as a function of the phase-leg control signals (u ref ), and
providing the cell control signals to the semiconductor switches of the cells.

2. The method of claim 1 ,
wherein the method comprises:
generating first side current reference signals (i g,ref ) depending on the mode control signals (MCS) by a first side control module of the control arrangement, and
generating the balance voltage reference signals (u bal,ref ) by a current control module of an inner control module of the control arrangement depending on the first side current reference signals (i g,ref ), the second side current reference signals (i m,ref ) and current balance reference signals (i bal,ref ).

3. The method of claim 1 ,
wherein the method comprises generating the balance voltage reference signals (u bal,ref ) by a current control module of the inner control module of the control arrangement depending on first side current reference signals (i g,ref ), the second side current reference signals (i m,ref ), the mode control signals (MCS) and the current balance reference signals (i bal,ref ).

4. The method of claim 1 ,
wherein the method comprises:
generating the current balance reference signals (i bal,ref ) by a decoupling matrix module of the inner control module depending on current balance signals (i bal ),
generating the current balance signals (i bal ) by a voltage control module of the inner control module depending on clock signals (u pll ) and measured phase-leg capacitor signals (u CΣ,yxn ) measured at the cells of the number M of phase-legs, and

generating the clock signals (u pll ) as a function of the first side frequency (ω g ) and the second side frequency (ω m ) by the inner module.

5. The method of claim 1 ,
wherein in case the converter is set to the static synchronous compensator mode, the mode control signals (MCS) are generated as a function of a first, a second and a third evaluated current balance signal (i bal,e1 , i bal,e2 , i bal,e3 ), wherein the first evaluated current balance signal (i bal,e1 ) depends on current balance signals (i bal ) of phase-legs which are connected to a first terminal (a) of the first side of the converter,
wherein the second evaluated current balance signal (i bal,e2 ) depends on current balance signals (i bal ) of phase-legs which are connected to a second terminal (b) of the first side of the converter, and
wherein the third evaluated current balance signal (i bal,e3 ) depends on current balance signals (i bal ) of phase-legs which are connected to a third terminal (c) of the first side of the converter.

6. The method of claim 5 ,
wherein the method comprises:
generating the mode control signals (MCS) as a function of rescaled signals and clock signals (u pll ) by a multiplication module of the rescale module, and
generating the clock signals (u pll ) as a function of the first side frequency (ω g ) and the second side frequency (ω m ) by the inner control module.

7. The method of one of claim 1 ,
wherein in case the converter is set to the static synchronous compensator mode, the mode control signals (MCS) are generated as a function of common mode voltage signals, and wherein the common mode voltage signals are generated by a processing module of the control arrangement as a function of measured signals and comprise a common mode voltage amplitude (û G 0 ) and a common mode voltage angle (ϕ uG 0 ).

8. The method of claim 7 ,
wherein the method comprises calculating a value of the common mode voltage angle (ϕ uG 0 ) and a value of the common mode voltage amplitude (û G 0 ) by:

ϕ

u
⁢
G

0

=

a
⁢
tan
⁢

k
6

⁢

k
1

-

k
3

⁢

k
4

k
3

⁢

k
5

-

k
6

⁢

k
2

u
^

G
0

=

{

-

k
3

k
1

⁢
cos
⁢

Assignees

• Hitachi Energy Ltd

Inventors

• Christe Alexandre

Classifications

• H02M7/797

  using semiconductor devices only · CPC title

• H02M7/4835

  comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage · CPC title

• H02M5/271 Primary

  from a three phase input voltage · CPC title