Interleaved sub-sampling phased array receiver

Patent metadata

Field	Value
Publication number	US-12316022-B2
Application number	US-202117352394-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jun 21, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.

First claim

What is claimed is:

1. A phased array, comprising:
a clock stage configured to generate a plurality of shifted clock signals, each shifted clock signal of the plurality of shifted clock signals comprising a different phase;
a beamforming stage configured to generate a beamformed signal comprising a beam formed in a direction based on a plurality of summed signals; and
a plurality of slices, each slice of the plurality slices comprising:
a filter stage configured to generate a corresponding summed signal of the plurality of summed signals by filtering a portion of blocker and noise interference in a corresponding receive signal of a plurality of receive signals based on a plurality of blocking signals and the plurality of shifted clock signals; and
a feedback stage configured to generate the plurality of blocking signals based on the plurality of shifted clock signals and the corresponding summed signal, the plurality of blocking signals representative of the blocker and noise interference in the corresponding receive signal, wherein the feedback stage is further configured to:
generate a scaled signal based on the beamformed signal, wherein a phase and an amplitude of the scaled signal is based on a configuration of a corresponding slice of the plurality of slices; and
generate the plurality of blocking signals based on the plurality of shifted clock signals and a difference between the corresponding summed signal and the scaled signal.

2. The phased array of claim 1 , wherein the feedback stage is further configured to:
receive the beamformed signal, the corresponding summed signal, and the plurality of shifted clock signals.

3. The phased array of claim 1 , wherein the filter stage is further configured to:
receive the corresponding receive signal, the plurality of shifted clock signals, and the plurality of blocking signals; and
generate the corresponding summed signal by filtering the portion of the blocker and noise interference in the corresponding receive signal based on the plurality of blocking signals and the plurality of shifted clock signals.

4. The phased array of claim 3 , wherein the feedback stage further configured to:
receive the beamformed signal, the corresponding summed signal, and the plurality of shifted clock signals;
generate a scaled signal based on the beamformed signal, a phase and an amplitude of the scaled signal based on a configuration of the corresponding slice of the plurality of slices; and
generate the plurality of blocking signals based on the plurality of shifted clock signals and a difference between the corresponding summed signal and the scaled signal.

5. The phased array of claim 1 , wherein the filter stage comprises:
a first summer configured to:
receive the corresponding receive signal and the plurality of blocking signals; and
generate a blocker signal based on the corresponding receive signal and the plurality of blocking signals;
an analog to digital converter (ADC) stage configured to:
receive the blocker signal and the plurality of shifted clock signals; and
generate a plurality of digital blocker signals based on the blocker signal and the plurality of shifted clock signals;

a finite impulse response (FIR) filter configured to:
receive the plurality of digital blocker signals; and
generate a plurality of weighted signals based on the plurality of digital blocker signals and a pre-configured weighting configuration; and

a second summer configured to:
receive the plurality of weighted signals; and
generate the corresponding summed signal based on the plurality of weighted signals.

6. The phased array of claim 5 , wherein the ADC stage comprises a plurality of ADCs, each ADC of the plurality of ADCs configured to:
receive the blocker signal and a corresponding shifted clock signal of the plurality of shifted clock signals; and
generate a corresponding digital blocker signal of the plurality of digital blocker signals based on the corresponding shifted clock signal and the blocker signal.

7. The phased array of claim 1 , wherein the feedback stage comprises:
a complex scaling circuit configured to:
receive the beamformed signal; and
generate the scaled signal based on the beamformed signal and the configuration of the corresponding slice of the plurality of slices;

a difference amplifier configured to:
receive the scaled signal and the corresponding summed signal; and
generate a blocker/noise signal based on the difference between the scaled signal and the corresponding summed signal, the blocker/noise signal representative of the blocker and noise interference; and

a digital to analog converter (DAC) stage configured to:
receive the blocker/noise signal and the plurality of shifted clock signals; and
generate the plurality of blocking signals based on the blocker/noise signal and the plurality of shifted clock signals.

8. The phased array of claim 7 , wherein the DAC stage comprises a plurality of DACs, each DAC of the plurality of DACs configured to:
receive the blocker/noise signal and a corresponding shifted clock signal of the plurality of shifted clock signals; and
generate a corresponding blocking signal of the plurality of blocking signals based on the corresponding shifted clock signal and the blocker/noise signal.

9. The phased array of claim 1 , wherein the corresponding receive signal is at a first frequency and the clock stage comprises a multi-phase clock generator configured to:
receive a clock signal at a second frequency that is a sub-harmonic frequency of the first frequency; and
generate the plurality of shifted clock signals at the second frequency based on the clock signal.

10. The phased array of claim 1 , wherein the beamforming stage comprises a beamformer configured to:
receive the plurality of summed signals, wherein a summed signal of the plurality of summed signals is received for each slice of the plurality of slices; and
generate the beamformed signal based on the plurality of summed signals.

11. A base station, comprising:
a clock stage configured to generate a plurality of shifted clock signals, each shifted clock signal of the plurality of shifted clock signals comprising a different phase;
a beamforming stage configured to generate a beamformed signal comprising a beam formed in a direction based on a plurality of summed signals; and
a plurality of slices, each slice of the plurality slices comprising:
a filter stage electrically coupled to the clock stage and the beamforming stage, the filter stage configured to generate a corresponding summed signal of the plurality of summed signals by filtering a portion of blocker and noise interference in a corresponding receive signal of a plurality of receive signals; and
a feedback stage electrically coupled to the clock stage, the filter stage, and the beamforming stage, the feedback stage configured to generate a plurality of blocking signals representative of the blocker and noise interference in the corresponding receive signal based on the plurality of shifted clock signals and the corresponding summed signal, wherein the feedback stage is further configured to:
generate a scaled signal based on the beamformed signal, wherein a phase and an amplitude of the scaled signal is based on a configuration of a corresponding slice of the plurality of slices; and
generate the plurality of blocking signals based on the plurality of shifted clock signals and a difference between the corresponding summed signal and the scaled signal.

12. The base station of claim 11 , wherein the filter stage comprises:
a first summer configured to:
receive the corresponding receive signal and

Assignees

• Intel Corp

Inventors

• Jann Benjamin
• Ravi Ashoke

Classifications

• H01Q3/2605

  Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays · CPC title

• H04B7/0848

  Joint weighting · CPC title

• H04L7/08

  the synchronisation signals recurring cyclically · CPC title

• H03H2017/0081

  of FIR filters · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title