Method and apparatus for improved memory module supply current surge response

Patent metadata

Field	Value
Publication number	US-12315588-B2
Application number	US-202117369851-A
Country	US
Kind code	B2
Filing date	Jul 7, 2021
Priority date	Jul 7, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) to generate a supply voltage for a memory module. The PMIC is to perform a measurement during bring-up of the memory module of a worst case current draw of the memory module and/or corresponding droop in the supply voltage. The PMIC is to apply a step-up to the supply voltage in accordance with the measurement in response to detection by the PMIC of a surge in the memory module's current draw during operation of the memory module.

First claim

The invention claimed is:

1. An apparatus, comprising:
a power management integrated circuit (PMIC) to generate a supply voltage for a memory module, the PMIC to perform a measurement during bring-up of the memory module of a worst case current draw of the memory module and/or corresponding droop in the supply voltage, the PMIC to apply a step-up to the supply voltage in accordance with the measurement in response to detection by the PMIC of a surge in the memory module's current draw during operation of the memory module.

2. The apparatus of claim 1 wherein the step-up negates the droop.

3. The apparatus of claim 1 wherein the step-up causes the supply voltage to remain closer to a nominal value during the surge than a value that is 16.7% higher than the nominal value.

4. The apparatus of claim 1 wherein the memory module is a dual in-line memory module.

5. The apparatus of claim 1 wherein the step-up is determined in view of a type of the memory module.

6. The apparatus of claim 5 wherein the step-up is determined in view of a supplier of the memory module.

7. The apparatus of claim 1 wherein the PMIC includes register space into which the measurement is to be recorded by the PMIC.

8. An apparatus, comprising:
a memory controller to communicate with a PMIC that is integrated on a memory module that the memory controller is to be coupled to, the memory controller to:
perform a look-up into information that lists step-up voltages for memory modules based at least on memory module type, the look-up to determine a step-up voltage for the memory module;
send to the PMIC the step-up voltage that the PMIC is to apply to a supply voltage provided to the memory module by the PMIC in response to detection by the PMIC of a surge of supply current drawn by the memory module during operation of the memory module.

9. The apparatus of claim 8 wherein the memory controller is to be coupled to the memory module by way of a memory channel that is compliant with a Joint Electron Device Engineering Council (JEDEC) specification.

10. The apparatus of claim 9 wherein the JEDEDC specification is a DDR5 JEDEC specification.

11. The memory controller of claim 8 wherein the memory controller is to receive a measurement performed by the PMIC of the memory module's worst case current draw and/or corresponding droop in the supply voltage.

12. The apparatus of claim 8 wherein the step-up causes the supply voltage to remain closer to a nominal value during the surge than a value that is 16.7% higher than the nominal value.

13. The apparatus of claim 8 wherein the memory module is a dual in-line memory module.

14. The apparatus of claim 8 wherein the step-up voltage is also determined in view of a supplier of the memory module.

15. A computing system, comprising:
a processor;
a network interface;
a memory including a memory module having a PMIC, the PMIC to provide a supply voltage to the memory module;
a memory controller coupled between the memory and the processor; and,
a storage medium containing program code that when processed by the processor causes the processor to perform a method, comprising:
performing a look-up into information that lists step-up voltages for memory modules based at least on memory module type, the look-up determining a step-up voltage for the memory module;
causing the step-up voltage to be communicated to the PMIC so that the PMIC will apply the step-up to the supply voltage in response to detection by the PMIC of a current surge by the memory module during operation of the memory module.

16. The computing system of claim 15 wherein the information further lists the step-up voltages based on a worst case current draw of the memory module and/or corresponding droop in the supply voltage, the PMIC to perform a measurement to determine the worst case current draw and/or corresponding droop in the supply voltage, the look-up to be performed with a result of the measurement that is provided by the PMIC.

17. The computing system of claim 15 wherein the information further lists the step-up voltages based on memory module supplier.

18. The computing system of claim 15 wherein the memory module is a DIMM.

19. The computing system of claim 15 wherein the step-up voltage causes the supply voltage to remain closer to a nominal value during the current surge than a value that is 16.7% higher than the nominal value.

Assignees

• Intel Corp

Inventors

• Heymann Douglas
• Vergis George

Classifications

• G05F1/465 Primary

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title