Memory device including sense amplifying circuit

Patent metadata

Field	Value
Publication number	US-12315579-B2
Application number	US-202318333756-A
Country	US
Kind code	B2
Filing date	Jun 13, 2023
Priority date	Jan 11, 2023
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A memory device includes a sense amplifying circuit coupled between a pull-up voltage line and a pull-down voltage line and configured to sense and amplify data of bit lines according to a sensing control signal; a fail detection circuit configured to calculate counting values of fail bits for each temperature based on the data and configured to generate a minimum error code for each temperature by detecting a minimum value for each temperature from the counting values for each temperature, in response to a test mode signal; and a sense amplifying control circuit configured to drive the pull-up voltage line and the pull-down voltage line by generating a pull-up voltage and a pull-down voltage corresponding to current temperature information based on the minimum error code for each temperature and configured to generate the sensing control signal according to the test mode signal.

First claim

What is claimed is:

1. A memory device, comprising:
a sense amplifying circuit coupled between a pull-up voltage line and a pull-down voltage line and configured to sense and amplify data of bit lines according to a sensing control signal;
a fail detection circuit configured to calculate counting values of fail bits for each temperature based on the data and configured to generate a minimum error code for each temperature by detecting a minimum value for each temperature from the counting values for each temperature, in response to a test mode signal; and
a sense amplifying control circuit configured to drive the pull-up voltage line and the pull-down voltage line by generating a pull-up voltage and a pull-down voltage corresponding to current temperature information based on the minimum error code for each temperature and configured to generate the sensing control signal according to the test mode signal.

2. The memory device of claim 1 , wherein the sense amplifying control circuit is configured to generate the sensing control signal to apply a test write voltage to the bit lines according to the test mode signal.

3. The memory device of claim 1 ,
wherein the minimum error code for each temperature includes a first minimum error code for a high temperature and a second minimum error code for a low temperature, and
wherein the fail detection circuit is configured to:
generate the first minimum error code by calculating the counting values for the high temperature and detecting the minimum value for the high temperature during a high-temperature test operation, and
generate the second minimum error code by calculating the counting values for the low temperature and detecting the minimum value for the low temperature during a low-temperature test operation.

4. The memory device of claim 3 , wherein the sense amplifying control circuit is configured to generate the pull-up voltage and the pull-down voltage corresponding to the current temperature information in a voltage range defined by the first minimum error code and the second minimum error code.

5. The memory device of claim 1 , wherein the fail detection circuit includes:
a fail counting circuit configured to calculate the counting values by comparing the data with a preset test pattern on a bit-by-bit basis in response to the test mode signal;
a per-temperature fail storage circuit configured to:
generate and store a plurality of code combinations by combining a pull-up code and a pull-down code,
store, as high-temperature counting values, the counting values corresponding to the respective code combinations during a high-temperature test operation, and
store, as low-temperature counting values, the counting values corresponding to the respective code combinations during a low-temperature test operation; and

an information generation circuit configured to output a first minimum error code by comparing the high-temperature counting values with one another, and a second minimum error code by comparing the low-temperature counting values with one another.

6. The memory device of claim 5 ,
wherein the fail detection circuit further includes a voltage code storage circuit configured to store the pull-up code corresponding to a plurality of preliminary pull-up voltages and the pull-down code corresponding to a plurality of preliminary pull-down voltages, and
wherein the preliminary pull-up voltages are set according to a voltage range of the pull-up voltage, and the preliminary pull-down voltages are set according to a voltage range of the pull-down voltage.

7. The memory device of claim 5 , wherein the fail counting circuit includes:
a test pattern storage configured to store the preset test pattern;
a comparator configured to output a pass/fail signal by comparing the data with the preset test pattern on a bit-by-bit basis; and
a fail bit counter configured to count the pass/fail signal to generate the counting values.

8. The memory device of claim 5 , wherein the information generation circuit is configured to:
output, as the first minimum error code, a code combination corresponding to a minimum one of the high-temperature counting values, and
output, as the second minimum error code, a code combination corresponding to a minimum one of the low-temperature counting values.

9. The memory device of claim 1 ,
wherein the minimum error code for each temperature includes a first minimum error code for a high temperature and a second minimum error code for a low temperature, and
wherein the sense amplifying control circuit includes:
a reference voltage generation circuit configured to:
generate first and second high-temperature reference voltages based on the first minimum error code, and
generate first and second low-temperature reference voltages based on the second minimum error code;

a voltage control circuit configured to:
generate the pull-up voltage corresponding to the current temperature information based on the first high-temperature reference voltage and the first low-temperature reference voltage, and
generate the pull-down voltage corresponding to the current temperature information based on the second high-temperature reference voltage and the second low-temperature reference voltage; and

a sensing control circuit configured to:
drive the pull-up voltage line and the pull-down voltage line respectively according to the pull-up voltage and the pull-down voltage, and
generate the sensing control signal according to the test mode signal.

10. The memory device of claim 9 , wherein the voltage control circuit includes:
a first reference voltage regulator configured to generate a pull-up reference voltage corresponding to the current temperature information based on the first high-temperature reference voltage and the first low-temperature reference voltage;
a first voltage generator configured to generate the pull-up voltage based on the pull-up reference voltage;
a second reference voltage regulator configured to generate a pull-down reference voltage corresponding to the current temperature information based on the second high-temperature reference voltage and the second low-temperature reference voltage; and
a second voltage generator configured to generate the pull-down voltage based on the pull-down reference voltage.

11. The memory device of claim 10 ,
wherein the first reference voltage regulator includes a plurality of resistors coupled in series between the first high-temperature reference voltage and the first low-temperature reference voltage and is configured to select one of the plurality of resistors according to the current temperature information to output the pull-up reference voltage, and
wherein the second reference voltage regulator includes a plurality of resistors coupled in series between the second high-temperature reference voltage and the second low-temperature reference voltage and is configured to select one of the plurality of resistors according to the current temperature information to output the pull-down reference voltage.

12. The memory device of claim 9 , wherein the sensing control circuit includes:
a control signal generation circuit configured to generate the sensing control signal according to the test mode signal;
a drive control circuit configured to output the pull-up voltage as a pull-up control signal and output the pull-down voltage as a pull-down control signal, in response to the sensing control signal; and
a voltage line driving circuit configured to drive the pull-up voltage line according to the pull-up control signal and drive the pull-down voltage line according to the pull-down control signal.

Assignees

• Sk Hynix Inc

Inventors

• Jang Yeonsu
• Kim Woongrae
• Yoon Jung Min

Classifications

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C2029/5002

  Characteristic · CPC title

• G11C29/46

  Test trigger logic · CPC title