Memory and method of operation with dummy and loaded route

Patent metadata

Field	Value
Publication number	US-12315557-B2
Application number	US-202318169167-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	Sep 15, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

First claim

What is claimed is:

1. A memory, comprising:
a storage cell array;
a write driver, coupled to the storage cell array and configured to transmit a data signal to be written to the storage cell array according to a received write operation command; and
a first column decoder, coupled to a first storage cell area of the storage cell array via a first column selection line and configured to perform a write operation on the storage cell array,
the first column selection line comprising a dummy route and a loaded route;
the dummy route being coupled to the first column decoder and the loaded route and being configured to transmit a first column selection signal to the loaded route,
the loaded route being coupled to the first storage cell area and being configured to transmit the first column selection signal to the first storage cell area, the first column selection signal being configured to select a storage cell column, on which the write operation is performed, from the first storage cell area,
wherein a transmission direction of the data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route;
wherein the memory cell array comprises a second storage cell area and the first storage cell area arranged in parallel along a first direction, wherein the first direction is a direction along which the write driver, the storage cell array and the first column decoder are successively arranged,
the dummy route is located in the first storage cell area and is configured to transmit the first column selection signal to the loaded route in a second direction opposite to the first direction, and
the loaded route is coupled to the first storage cell area and is configured to transmit the first column selection signal to the first storage cell area in the first direction, wherein the first column selection signal is configured to select the storage cell column, on which the write operation is performed, from the first storage cell area.

2. The memory of claim 1 , wherein the memory further comprises a second column decoder, the second column decoder and the first column decoder being located on two opposite sides of the storage cell array, and the second column decoder and the write driver being located on a same side of the storage cell array,
wherein the second column decoder is coupled to the second storage cell area and is configured to perform a write operation on the second storage cell area.

3. The memory of claim 2 , wherein the memory further comprises a second column selection line which is coupled to the second column decoder and the second storage cell area, and is configured to transmit a second column selection signal to the second storage cell area, wherein the second column selection signal is configured to select a storage cell column, on which the write operation is performed, from the second storage cell area.

4. The memory of claim 1 , further comprising:
a command decoder, coupled to the first column decoder and configured to control, according to the received write operation command, the first column decoder to perform the write operation.

5. The memory of claim 1 , wherein the memory comprises a dynamic random access memory.

6. A method for operating a memory, wherein the memory comprises a storage cell array, a write driver, a first column decoder and a first column selection line, the first column selection line comprises a dummy route and a loaded route and the first column decoder is coupled to the storage cell array via the dummy route and the loaded route,
the method for operating the memory comprises:
transmitting, by the write driver, a data signal to be written to a first storage cell area of the storage cell array according to a received write operation command;
transmitting, by the first column decoder, a first column selection signal to the loaded route via the dummy route; and
transmitting, via the loaded route, the first column selection signal to the first storage cell area, the first column selection signal being configured to select a storage cell column, on which a write operation is performed, from the first storage cell area,
wherein a transmission direction of the data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route;
wherein the memory cell array comprises a second storage cell area and the first storage cell area arranged in parallel along the first direction, the first direction is a direction along which the write driver, the storage cell array and the first column decoder are successively arranged, and the method comprises:
transmitting, by the first column decoder via the dummy route, the first column selection signal to the loaded route in a second direction opposite to the first direction, wherein the dummy route is located in the first storage cell area; and
transmitting, via the loaded route, the first column selection signal to the first storage cell area in the first direction, wherein the loaded route is coupled to the first storage cell area, and the first column selection signal is configured to select the storage cell column, on which the write operation is performed, from the first storage cell area.

7. The method for operating a memory of claim 6 , wherein the memory further comprises a second column decoder, the second column decoder and the first column decoder are located on two opposite sides of the storage cell array, and the second column decoder and the write driver are located on a same side of the storage cell array,
the method further comprises:
performing, by the second column decoder, a write operation on the second storage cell area.

8. The method for operating a memory of claim 7 , wherein the memory further comprises a second column selection line,
performing, by the second column decoder, the write operation on the second storage cell area, comprising:
transmitting, via the second column selection line, a second column selection signal to the second storage cell area, wherein the second column selection signal is configured to select a storage cell column, on which the write operation is performed, from the second storage cell area.

9. The method for operating a memory of claim 6 , wherein the memory further comprises a command decoder, the method further comprises:
controlling, by the command decoder according to a received write operation command, the first column decoder to perform the write operation.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C8/10

  Decoders · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C7/1093

  Input synchronization · CPC title