Display panel, driving circuit and display device for ameliorating color cast phenomenon

Patent metadata

Field	Value
Publication number	US-12315443-B2
Application number	US-202318109418-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	Nov 30, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

The present disclosure discloses a display panel, a driving circuit and a display device. The display panel includes a pixel circuit and a light-emitting element. A data writing cycle of the pixel circuit includes a data writing phase and m holding phases. In the data writing phase, the first scan signal includes at least one first valid pulse. A light emission control signal includes one second valid pulse in the data writing phase and in each holding phase. The working modes of the display panel includes a first mode. In the first mode, the interval between the start time of the first valid pulse in the (i+1)-th data writing cycle and the end time of the last second valid pulse in the i-th data writing cycle is t 1 , and in the data writing phase, the duration of the light emission control signal being an invalid pulse is t 2 ,
t ⁢ 1 t ⁢ 2 ≥ 1 ⁢ % , m ≥ 1 , i ≥ 1 ,
and m and i are integers.

First claim

What is claimed is:

1. A display panel, comprising:
a pixel circuit; and
a light-emitting element,
wherein:
the pixel circuit includes a light emission control module, and the light emission control module is configured to make the light-emitting element emit light under control of a light emission control signal;
the pixel circuit includes a first pixel circuit, the first pixel circuit includes a first reset module, the light-emitting element includes a first light-emitting element that emits light of a first color, and the first reset module provides a first reset signal to the first light-emitting element under control of a first scan signal;
a data writing cycle of the pixel circuit includes a data writing phase and m holding phases;
in the data writing phase, the first scan signal includes at least one first valid pulse;
the light emission control signal includes one second valid pulse in the data writing phase and in each of the holding phases;
working modes of the display panel include a first mode, wherein in the first mode, an interval between a start time of a first valid pulse in an (i+1)-th data writing cycle and an end time of a last second valid pulse in an i-th data writing cycle is t 1 , and in the data writing phase, a duration of the light emission control signal being an invalid pulse is t 2 , t 1 /t 2 ≥1%, m≥1, i≥1, and m and i are integers;
the pixel circuit further comprises a second pixel circuit, the second pixel circuit includes a second reset module, the light-emitting element includes a second light-emitting element that emits light of a second color, and the second reset module transmits a second reset signal to the second light-emitting element under control of a second scan signal;
in the data writing phase, the second scan signal includes at least one third valid pulse; and
in the first mode, an interval between a start time of the first third valid pulse in the (i+1)-th data writing cycle and an end time of a last second valid pulse in the i-th data writing cycle is t 5 , and t 1 ≠t 5 .

2. The display panel according to claim 1 , wherein:

t
⁢
1

t
⁢
2

≥

50
⁢

%
.

3. The display panel according to claim 1 , wherein:
in the first mode, an interval between an end time of the first valid pulse in the (i+1)-th data writing cycle and a start time of a first second valid pulse in the (i+1)-th data writing cycle is t 3 , and t 1 >t 3 .

4. The display panel according to claim 3 , wherein:
t 3 >0.

5. The display panel according to claim 4 , wherein:
t 3 ≥0.5H, wherein the display panel comprises n rows of pixel circuits, a refresh rate of the display panel in the first mode is F, and

H
=

1

F
×
n

.

6. The display panel according to claim 3 , wherein:
t 3 =0.

7. The display panel according to claim 1 , wherein:
a duration of the first valid pulse is t 4 , and

t
⁢
2

t
⁢
4

≥
10.

8. The display panel according to claim 1 , wherein:
t 1 >t 5 .

9. The display panel according to claim 1 , wherein:
a duration of the first valid pulse is t 4 , a duration of the third valid pulse is t 6 , and t 4 =t 6 .

10. The display panel according to claim 1 , wherein:
the second reset module provides the second reset signal to the second light-emitting element under control of the first scan signal.

11. The display panel according to claim 1 , wherein:
in at least one of the holding phases, the first scan signal includes at least one fourth valid pulse; and
in a same data writing cycle, a second valid pulse in a j-th holding phase is a (j+1)-th second valid pulse, and an interval between a start time of a first fourth valid pulse in the j-th holding phase and an end time of the j-th second valid pulse is t 7 , t 1 =t 7 , wherein, 1≤j≤m.

12. The display panel according to claim 1 , wherein:
in at least one of the holding phases, the first scan signal includes at least one fourth valid pulse; and
in a same data writing cycle, a second valid pulse in a j-th holding phase is a (j+1)-th second valid pulse, and an interval between a start time of a first fourth valid pulse in the j-th holding phase and an end time of the j-th second valid pulse is t 7 , t 1 ≠t 7 , wherein, 1≤j≤m.

13. The display panel according to claim 12 , wherein:
t 7 <t 1 .

14. The display panel according to claim 11 , wherein:
a duration of the first valid pulse is t 4 , a duration of the fourth valid pulse is t 8 , and t 4 =t 8 .

15. The display panel according to claim 1 , wherein:
in the data writing phase, the first scan signal includes at least two first valid pulses.

16. A display panel, comprising:
a pixel circuit; and
a light-emitting element,
wherein:
the pixel circuit includes a light emission control module, the light emission control module is configured to make the light-emitting element emit light under control of a light emission control signal;
the pixel circuit includes a first pixel circuit, the first pixel circuit includes a first reset module, the light-emitting element includes a first light-emitting element that emits light of a first color, and the first reset module provides a first reset signal to the first light-emitting element under control of a first scan signal;
a data writing cycle of the pixel circuit includes a data writing phase and m holding phases;
in the data writing phase, the first scan signal includes at least one first valid pulse;
the light emission control signal includes one second valid pulse in the data writing phase and in each of the holding phases;
working modes of the display panel include a first mode, wherein in the first mode, an interval between a start time of a first valid pulse in an (i+1)-th data writing cycle and an end time of a last second valid pulse in the i-th data writing cycle is t 1 ,

t
⁢
1

≥

1
⁢
H

,

H
=

1

F
×
n

,

 n is the number of rows of pixel circuits, F is a refresh rate of the display

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Zhang Di
• Xiang Dongxu

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0294

  Details of sampling or holding circuits arranged for use in a driver for data electrodes · CPC title

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title