Pixel circuit, drive method therefor, display substrate, and display device

Patent metadata

Field	Value
Publication number	US-12315430-B2
Application number	US-202218029106-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	Jun 21, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A pixel circuit, a driving method therefor, a display substrate and a display device are provided. The pixel circuit includes a drive circuit and a light emitting element connected in series between a first power supply terminal and a third power supply terminal; the drive circuit is used for providing a drive current and controlling a time length of conduction of a current path between the first power supply terminal and the third power supply terminal; the light emitting element is used for receiving the drive current in the current path and emitting light; the drive circuit includes a drive control sub-circuit, a light emitting control sub-circuit and a time-length control sub-circuit; the drive control sub-circuit is used for providing a drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node.

First claim

The invention claimed is:

1. A pixel circuit comprising: a drive circuit and a light emitting element connected in series between a first power supply terminal and a third power supply terminal; the drive circuit is configured to provide a drive current and control a time length of conduction of a current path between the first power supply terminal and the third power supply terminal; the light emitting element is configured to receive the drive current in the current path and emit light; the drive circuit comprises a drive control sub-circuit, a light emitting control sub-circuit and a time-length control sub-circuit;
the drive control sub-circuit is electrically connected with a first scan signal terminal, a first data signal terminal, a first node and a second node respectively, and is configured to provide the drive current to the first node under control of the first scan signal terminal, the first data signal terminal and the second node;
the light emitting control sub-circuit is electrically connected with a light emitting signal terminal, the first power supply terminal and the second node respectively, and is configured to provide a signal of the first power supply terminal to the second node under control of the light emitting signal terminal;
the time-length control sub-circuit is electrically connected with a second scan signal terminal, a second data signal terminal, a second power supply terminal, the first node and a third node respectively, and is configured to provide a signal of the first node to the third node under control of the second scan signal terminal and the second data signal terminal; and
the light emitting element is electrically connected with the third node and the third power supply terminal respectively.

2. The pixel circuit according to claim 1 , wherein when a signal of the first scan signal terminal is an effective level signal, a signal of the second scan signal terminal is an effective level signal, and a signal of the light emitting signal terminal is an ineffective level signal;
when the signal of the light emitting signal terminal is an effective level signal, the signals of the first scan signal terminal and the second scan signal terminal are ineffective level signals.

3. The pixel circuit according to claim 2 , wherein the drive control sub-circuit is further electrically connected with a third scan signal terminal, is configured to provide a drive current to the first node under control of the first scan signal terminal, the third scan signal terminal, the first data signal terminal and the second node;
when the signal of the first scan signal terminal is an effective level signal, a signal of the third scan signal terminal is an effective level signal; and
when the signal of the light emitting signal terminal is an effective level signal, the signal of the third scan signal terminal is an ineffective level signal.

4. The pixel circuit according to claim 3 , wherein the drive control sub-circuit comprises: a first transistor, a second transistor, a third transistor, and a first capacitor;
a control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node;
a control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node;
a control electrode of the third transistor is electrically connected with the third scan signal terminal, a first electrode of the third transistor is electrically connected with the first data signal terminal, and a second electrode of the third transistor is electrically connected with the fourth node;
one plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node; and
the second transistor and the third transistor are of different transistor types.

5. The pixel circuit according to claim 2 , further comprising: a reset sub-circuit and/or a node control sub-circuit;
the reset sub-circuit is electrically connected with a reset signal terminal, an initial signal terminal and the third node respectively, and is configured to provide a signal of the initial signal terminal to the third node under control of the reset signal terminal;
the node control sub-circuit is electrically connected with the first scan signal terminal, a control signal terminal and the first node respectively, and is configured to provide a signal of the control signal terminal to the first node or read the signal of the first node to the control signal terminal under control of the first scan signal terminal, wherein a voltage value of the signal of the control signal terminal is constant.

6. The pixel circuit according to claim 5 , wherein when a signal of the reset signal terminal is an effective level signal, signals of the first scan signal terminal, the second scan signal terminal and the light emitting signal terminal are ineffective level signals;
when the signal of the first scan signal terminal is an effective level signal, the signal of the reset signal terminal is an ineffective level signal; and
when the signal of the light emitting signal terminal is an effective level signal, the signal of the reset signal terminal is an ineffective level signal.

7. The pixel circuit according to claim 5 , wherein the reset sub-circuit comprises: a seventh transistor;
a control electrode of the seventh transistor is electrically connected with the reset signal terminal, a first electrode of the seventh transistor is electrically connected with the initial signal terminal, and a second electrode of the seventh transistor is electrically connected with the third node; or
wherein the node control sub-circuit comprises: an eighth transistor; and
a control electrode of the eighth transistor is electrically connected with the first scan signal terminal, a first electrode of the eighth transistor is electrically connected with the control signal terminal, and a second electrode of the eighth transistor is electrically connected with the first node.

8. The pixel circuit according to claim 1 , wherein the drive control sub-circuit comprises: a first transistor, a second transistor, and a first capacitor;
a control electrode of the first transistor is electrically connected with a fourth node, a first electrode of the first transistor is electrically connected with the second node, and a second electrode of the first transistor is electrically connected with the first node;
a control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode of the second transistor is electrically connected with the first data signal terminal, and a second electrode of the second transistor is electrically connected with the fourth node; and
one plate of the first capacitor is electrically connected with the fourth node, and the other plate of the first capacitor is electrically connected with a fourth power supply terminal or the first node.

9. The pixel circuit according to claim 1 , wherein the light emitting control sub-circuit comprises a fourth transistor;
a control electrode of the fourth transistor is electrically connected with the light emitting signal terminal, a first electrode of the fourth transistor is electrically connected with the first power supply terminal,

Assignees

• Boe Technology Group Co Ltd

Inventors

• Niu Jinfei
• Xuan Minghua
• Zhang Can
• Wang Can
• Cong Ning
• Zhang Jingjing
• Bai Xiao

Classifications

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title