Stalling issue queue entries until consecutive allocated entries are available for segmented stores

Patent metadata

Field	Value
Publication number	US-12314718-B2
Application number	US-202318115971-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Dec 2, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A method for performing segmented vector store operations is disclosed. The method includes decoding one or more segmented vector store micro-operations (uops) of segmented vector store instruction in a pipeline, allocating, based on each of the one or more segmented vector store uops, one or more respective store buffer entries in First-in, First-out (FIFO) order, stalling the pipeline until store buffer entries are allocated by all of segmented vector store uops of the segmented vector store instruction, and writing, based on each of the one or more segmented vector store uops, manipulated vector data into multiple store buffer entries.

First claim

What is claimed is:

1. A method comprising:
decoding one or more segmented vector store micro-operations (uops) of segmented vector store instruction in a pipeline;
allocating, based on each of the one or more segmented vector store uops, one or more respective store buffer entries in first-in, first-out (FIFO) order;
stalling the pipeline until store buffer entries are allocated for all of the one or more segmented vector store uops of the segmented vector store instruction;
writing, based on each of the one or more segmented vector store uops, manipulated vector data into allocated store buffer entries; and
allocating, using a virtual bit, a virtual index to the store buffer entries.

2. The method of claim 1 , wherein stalling the pipeline until store buffer entries are allocated to all of the one or more segmented vector store uops includes:
stalling each segmented vector store uop before performing vector operation and until a respective store buffer entry for a last vector store uop becomes available.

3. The method of claim 2 , wherein each of the segmented vector store uops has a payload that includes a respective virtual index of a respective store buffer entry allocated for a first segmented vector store uop of the segmented vector store instruction, and a total number of store buffer entries allocated for all of the segmented vector store uops.

4. The method of claim 3 , wherein stalling the pipeline until store buffer entries are allocated for all of the one or more segmented vector store uops further includes:
determining the respective virtual index of the last segmented vector store uop based on the respective virtual index of the first segmented vector store uop and the total number of the store buffer entries allocated.

5. The method of claim 4 , wherein allocating one or more respective store buffer entries in first-in, first-out (FIFO) order is managed by an allocation pointer that points to a next store buffer entry to be allocated.

6. The method of claim 5 , further comprising:
deallocating, after the one or more segmented vector store uops retire from the pipeline, respective store buffer entries.

7. The method of claim 5 , further comprising:
deallocating, after all segmented vector store uops retire from the pipeline, the store buffer entries.

8. The method of claim 6 , wherein the store buffer entries are deallocated in a program order.

9. The method of claim 8 , wherein deallocating is managed by a retirement pointer to point to a next register entry to be retired.

10. A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:
a processor including circuitry that:
decodes one or more segmented vector store micro-operations (uops) of segmented vector store instruction in a pipeline;
allocates, based on each of the one or more segmented vector store uops, one or more respective store buffer entries in a first-in, first-out (FIFO) order;
stalls the pipeline until store buffer entries are allocated for all of the one or more segmented vector store uops of the segmented vector store instruction;
writes, based on each of the one or more segmented vector store uops, manipulated vector data into allocated store buffer entries; and
allocate, using a virtual bit, a virtual index to the store buffer entries.

11. The non-transitory computer readable medium of claim 10 , wherein
stalling the pipeline until the store buffer entries are allocated for all of the segmented vector store uops includes:
stalling each segmented vector store uop before performing a vector operation and until a respective store buffer entry for a last segmented vector store uop becomes available.

12. The non-transitory computer readable medium of claim 11 , wherein each of the segmented vector store uops has a payload that includes a respective virtual index of respective store buffer entry allocated for a first segmented vector store uop of the segmented vector store instruction, and a total number of store buffer entries allocated for all of the segmented vector store uops.

13. The non-transitory computer readable medium of claim 12 , wherein stalling the pipeline until store buffer entries are allocated for all of segmented vector store uops includes:
determining the respective virtual index of the last segmented vector store uop based on the respective virtual index of the first segmented vector store uop and the total number of the store buffer entries allocated.

14. An integrated circuit comprising:
a store buffer; and
a processor configured to:
decode one or more segmented vector store micro-operations (uops) of segmented vector store instruction in a pipeline;
allocate, based on each of the one or more segmented vector store uops, respective store buffer entries in the store buffer in first-in, first out (FIFO) order;
stall the pipeline until store buffer entries are allocated for all of the one or more segmented vector store uops of the segmented vector store instruction;
write, based on each of the one or more segmented vector store uops, manipulated vector data into allocated store buffer entries; and
allocate, using a virtual bit, a virtual index to the store buffer entries.

15. The integrated circuit of claim 14 , wherein to stall the pipeline until the store buffer entries are allocated for all of the one or more segmented vector store uops includes:
stall each segmented vector store uop before performing a vector operation and until a respective store buffer entry for a last vector store uop becomes available.

16. The integrated circuit of claim 15 , wherein each of the segmented vector store uops has a payload that includes a respective virtual index of respective store buffer entry allocated for a first segmented vector store uop of the segmented vector store instruction, and a total number of store buffer entries allocated by all of the segmented vector store uops.

17. The integrated circuit of claim 16 , wherein to stall the pipeline until the store buffer entries are allocated for all of the one or more segmented vector store uops further includes:
determine the respective virtual index of the last segmented vector store uop based on the respective virtual index of the first segmented vector store uop and the total number of the store buffer entries allocated.

Assignees

• Sifive Inc

Inventors

• Smith Josh

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3814 Primary

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/3005 Primary

  to perform operations for flow control · CPC title