System, method and/device for managing memory devices

Patent metadata

Field	Value
Publication number	US-12314570-B2
Application number	US-202217814438-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Jul 22, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Briefly, embodiments, such as methods and/or systems for employing memory devices.

First claim

What is claimed is:

1. A method comprising:
receiving a first command to execute a write operation, the write operation to include writing to a non-volatile memory at least first symbol values at associated first symbol positions of a word;
determining, from a memory address specified in the received first command, a location in the non-volatile memory to store the word via the write operation;
selecting a mapping function based, at least in part, on the determined location;
mapping the first symbol values to second symbol values to be associated with second symbol positions according to the mapping function; and
executing the write operation at least in part by storing the second symbol values in the second symbol positions at the determined location,
wherein at least one first symbol value in at least one of the first symbol positions does not equal a second symbol value mapped to a corresponding one of the second symbol positions.

2. The method of claim 1 , and further comprising:
responsive to a second command to execute a read operation, mapping the stored second symbol values to third symbol values in third symbol positions based, at least in part, on the determined location.

3. The method of claim 2 , wherein the first symbol values in the first symbol positions match respective third symbol values in the third symbol positions.

4. The method of claim 1 , wherein mapping the first symbol values to the second symbol values comprises mapping the first symbol values to different symbol positions.

5. The method of claim 1 , wherein mapping the first symbol values to the second symbol values comprises inverting the first symbol values.

6. The method of claim 1 , and further comprising selecting a word address in the location to store the second symbol values based, at least in part, on a wear leveling operation.

7. The method claim 1 , and further comprising:
applying a plurality of reverse mapping functions to a word stored in the non-volatile memory to provide a plurality of results; and
determining the mapping function based, at least in part, on a match of at least one of the results with a test sequence.

8. The method of claim 1 , and further comprising:
accessing the non-volatile memory to obtain pointers determining a partition in the non-volatile memory; and
determining the mapping function based, at least in part, on the determined partition.

9. A device comprising:
a non-volatile memory; and
a memory controller to:
receive a first command to execute a write operation, the write operation to include writing to a non-volatile memory at least first symbol values at associated first symbol positions of a word;
determine, from a memory address specified in the received first command, a location in the non-volatile memory to store the word via the write operation;
select a mapping function based, at least in part, on the determined location;
map the first symbol values to second symbol values to be associated with second symbol positions according to the mapping function; and
execute the write operation at least in part by storing the second symbol values in the second symbol positions at the determined location,
wherein at least one first symbol value in at least one of the first symbol positions does not equal a second symbol value mapped to a corresponding one of the second symbol positions.

10. The device of claim 9 , wherein the memory controller is further to:
responsive to a second command to execute a read operation, map the stored second symbol values to third symbol values in third symbol positions based, at least in part, on the determined location.

11. The device of claim 10 , wherein the first symbol values in the first symbol positions match respective third symbol values in the third symbol positions.

12. The device of claim 9 , wherein the memory controller is further to map the first symbol values to the second symbol values by mapping the first symbol values to different symbol positions.

13. The device of claim 9 , wherein the memory controller is further to map the first symbol values to the second symbol values at least in part by inverting the first symbol values.

14. The device of claim 9 , wherein the memory controller is further to select a word address in the location to store the second symbol values based, at least in part, on a wear leveling operation.

15. The device of claim 9 , wherein the memory controller is further to:
apply a plurality reverse mapping functions to a word stored in the non-volatile memory to provide a plurality of results; and
determine the mapping function based, at least in part, on a match of at least one of the results with a test sequence.

16. The device of claim 9 , wherein the memory controller is further to:
access the non-volatile memory to obtain pointers determining a partition in the non-volatile memory; and
determine the mapping function based, at least in part, on the determined partition.

17. An article comprising:
a non-transitory storage medium comprising computer-readable instructions stored thereon that are executable by one or more processors of a computing device to:
express a memory controller, to be formed in a circuit device and to be coupled to a non-volatile memory, the memory controller to comprise:
circuitry receive a first command to execute a write operation, the write operation to include writing to a non-volatile memory at least first symbol values at associated first symbol positions of a word;
circuitry to determine, from a memory address specified in the received first command, a location in the non-volatile memory to store the word via the write operation;
circuitry to select a mapping function based, at least in part, on the determined location;
circuitry to map the first symbol values to second symbol values to be associated with second symbol positions according to the mapping function; and
circuitry to execute the write operation at least in part by storing the second symbol values in the second symbol positions at the determined location,
wherein at least one first symbol value in at least one of the first symbol positions does not equal a second symbol value mapped to a corresponding one of the second symbol positions.

18. The article of claim 17 , wherein the memory controller is further to comprise:
circuitry to, responsive to a second command to execute a read operation, map the stored second symbol values to third symbol values in third symbol positions based, at least in part, on the determined location.

19. The article of claim 18 , wherein the first symbol values in the first symbol positions match respective third symbol values in the third symbol positions.

20. The article of claim 17 , wherein the memory controller is further to comprise circuitry to map the first symbol values to the second symbol values by mapping the first symbol values to different symbol positions.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Gamage Sahan Sajeewa Hiniduma Udugama
• Redondo Fernando Garcia
• Švedas Jonas

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/1036

  Life time enhancement · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title