FIFO memory system and FIFO memory control method

Patent metadata

Field	Value
Publication number	US-12314197-B2
Application number	US-202218271865-A
Country	US
Kind code	B2
Filing date	Jul 1, 2022
Priority date	Jul 30, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.

First claim

What is claimed is:

1. A first-in, first-out (FIFO) memory system, the FIFO memory system comprising:
a FIFO memory;
a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals comprise a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and
a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range;
wherein a lower limit of the first range is not less than an upper limit of the second range,
wherein the controller is configured to generate a control word based on the data volume in the FIFO memory; and
the read clock frequency circuit is configured to output the first clock signal or the second clock signal based on the control word; wherein the first clock signal and the second clock signal both comprise a first frequency signal and a second frequency signal, probabilities of occurrence of the first frequency signal and the second frequency signal being controlled by the control word,
wherein the read clock frequency circuit comprises:
a frequency synthesizer, configured to generate a pulse signal based on reference pulse signals and the control word, the reference pulse signals being uniformly spaced in phase, the pulse signal being the first clock signal or the second clock signal;
wherein the control word comprises a first coefficient and a second coefficient; and
the pulse signal comprises the first frequency signal generated based on the reference pulse signals and the first coefficient, and the second frequency signal generated based on the reference pulse signals and the first coefficient, a proportion of the first frequency signal and the second frequency signal in the pulse signal being controlled by the second coefficient.

2. The FIFO memory system according to claim 1 , wherein the lower limit of the first range is a first threshold, an upper limit of the first range is a capacity of the FIFO memory, a lower limit of the second range is 0, and the upper limit of the second range is a second threshold, the first threshold being greater than the second threshold; and
the controller is further configured to control the clock signal output by the read clock frequency circuit to remain unchanged in a case that the data volume in the FIFO memory is in a third range, wherein a lower limit of the third range is the second threshold, and an upper limit of the third range is the first threshold.

3. The FIFO memory system according to claim 2 , wherein a ratio of a difference between the first threshold and the second threshold to the capacity of the FIFO memory is not less than 5% and not greater than 25%.

4. The FIFO memory system according to claim 3 , wherein the frequency of the first clock signal is greater than a frequency of a write clock of the FIFO memory, and the frequency of the second clock signal is less than the frequency of the write clock of the FIFO memory.

5. The FIFO memory system according to claim 1 , wherein the controller is configured to, in a case that the data volume in the FIFO memory is in the second range and a valid signal of the FIFO memory is at a low level, make a frequency of the second clock signal decrease according to a first law by controlling the generated control word to vary.

6. The FIFO memory system according to claim 1 , wherein the controller is configured to determine the data volume in the FIFO memory based on a flag bit output by the FIFO memory.

7. A FIFO memory control method, the method comprising:
determining a data volume in a FIFO memory; and
controlling a read clock frequency circuit to output a first clock signal as a read clock of the FIFO memory in a case that the data volume in the FIFO memory is in a first range, or controlling the read clock frequency circuit to output a second clock signal as the read clock of the FIFO memory in a case that the data volume in the FIFO memory is in a second range;
wherein a lower limit of the first range is not less than an upper limit of the second range,
wherein controlling the read clock frequency circuit to output the first clock signal as the read clock of the FIFO memory in the case that the data volume in the FIFO memory is in the first range, or controlling the read clock frequency circuit to output the second clock signal as the read clock of the FIFO memory in the case that the data volume in the FIFO memory is in the second range, comprises:
generating a control word based on the data volume in the FIFO memory; and
making the read clock frequency circuit output the first clock signal or the second clock signal based on the control word by outputting the control word to the read clock frequency circuit, wherein the first clock signal and the second clock signal both comprise a first frequency signal and a second frequency signal, probabilities of occurrence of the first frequency signal and the second frequency signal being controlled by the control word,
wherein the read clock frequency circuit comprises:
a frequency synthesizer, configured to generate a pulse signal based on reference pulse signals and the control word, the reference pulse signals being uniformly spaced in phase, the pulse signal being the first clock signal or the second clock signal;
wherein the control word comprises a first coefficient and a second coefficient; and
the pulse signal comprises the first frequency signal generated based on the reference pulse signals and the first coefficient, and the second frequency signal generated based on the reference pulse signals and the first coefficient, a proportion of the first frequency signal and the second frequency signal in the pulse signal being controlled by the second coefficient.

8. The method according to claim 7 , wherein the lower limit of the first range is a first threshold, an upper limit of the first range is a capacity of the FIFO memory, a lower limit of the second range is 0, and the upper limit of the second range is a second threshold, the first threshold being greater than the second threshold; and the method further comprises:
controlling the read clock of the FIFO memory to remain unchanged, in a case that the data volume in the FIFO memory is in a third range, wherein a lower limit of the third range is the second threshold, and an upper limit of the third range is the first threshold.

9. The method according to claim 7 , wherein generating the control word based on the data volume in the FIFO memory comprises:
in a case that the data volume in the FIFO memory is in a second range and a valid signal of the FIFO memory is at a low level, making a frequency of the second clock signal decrease according to a first law by controlling the generated control word to vary.

10. The method according to claim 7 , wherein determining the data volume in the FIFO memory comprises:
determining the data volume in the FIFO memory based on a flag bit output by the FIFO memory.

11. The method according to claim 8 , wherein a ratio of a difference between the first threshold and the second threshold to the capacity of the FIFO memory is not less than 5% and not greater than 25%.

12. The method according to claim 11 , wherein the frequency of the first clock signal is greater than a frequency of a write clock of the FIFO memory, and the frequency of the second clock signal is les

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• G06F13/1621

  by maintaining request order · CPC title

• G06F5/10

  having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory {(G06F5/065 takes precedence)} · CPC title

• G06F11/14

  Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16) · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title