Gated ring oscillator linearization

Patent metadata

Field	Value
Publication number	US-12314014-B2
Application number	US-202318466027-A
Country	US
Kind code	B2
Filing date	Sep 13, 2023
Priority date	Jul 30, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

First claim

What is claimed is:

1. An apparatus comprising:
a phase detector comprising:
a time-to-digital converter (TDC); and
an output coupled to an output of the TDC;

a processor coupled to the output of the phase detector;
an error computation circuit coupled to the processor; and
an oscillator coupled to the error computation circuit and to an input of the phase detector.

2. The apparatus of claim 1 , wherein the TDC is a gated ring oscillator (GRO) based TDC.

3. The apparatus of claim 1 , wherein the TDC is configured to generate a measurement result indicating a time between a first event and a second event of a signal.

4. The apparatus of claim 3 , wherein the TDC is further configured to provide a digital code representative of the measurement result.

5. The apparatus of claim 3 , wherein the processor is configured to:
compare the measurement result to a target value; and
determine a non-linearity model to correct a variance of the measurement result from the target value.

6. The apparatus of claim 5 , wherein the non-linearity model is implemented as a look-up table.

7. The apparatus of claim 5 , wherein the non-linearity model is implemented as a polynomial function.

8. The apparatus of claim 1 , wherein the phase detector comprises:
a first input for receiving a reference clock signal;
a second input;
a first multiplexer coupled to the first input; and
a second multiplexer coupled to the second input, wherein the TDC is coupled to an output of the first multiplexer and to an output of the second multiplexer.

9. The apparatus of claim 1 , further comprising a filter coupled to an output of the error computation circuit and to an input of the oscillator.

10. The apparatus of claim 1 , further comprising a multiplexer coupled to the output of the phase detector and to an output of the processor.

11. The apparatus of claim 1 , further comprising: a state machine coupled to the phase detector and to the processor.

12. The apparatus of claim 11 , wherein an output of the state machine is coupled to a control input of a first multiplexer of the phase detector, to a control input of a second multiplexer of the phase detector, and to the processor.

13. The apparatus of claim 11 , wherein the phase detector comprises:
a first multiplexer having a first input coupled to receive a reference clock signal, and a second input coupled to a first output of the state machine; and
a second multiplexer having a first input coupled to receive a feedback signal from the oscillator, and a second input coupled to a second output of the state machine.

14. The apparatus of claim 11 , wherein the state machine is configured to control a mode of operation of the phase detector.

15. The apparatus of claim 1 , wherein the error computation circuit is configured to compare a measurement result from the processor to an expected result to provide a phase error signal.

16. A method, comprising:
receiving a calibration signal;
measuring the calibration signal to provide a measurement result, the measurement result including variance from a target value;
processing the measurement result to determine a non-linearity model, the non-linearity model defining the variance of the measurement result from the target value;
receiving an operating mode signal;
measuring the operating mode signal to provide a second measurement result, the second measurement result including variance from a target value; and
processing the second measurement result according to the non-linearity model to compensate for the variance in the second measurement result from the target value.

17. The method of claim 16 , wherein the target value is a value indicative of a linear response.

18. The method of claim 16 , wherein the non-linearity model is implemented as a look-up table.

19. The method of claim 16 , wherein the non-linearity model is implemented as a polynomial function.

20. The method of claim 16 , wherein the calibration signal and the operating mode signal are received by a gated ring oscillator (GRO) based TDC.

Assignees

• Texas Instruments Inc

Inventors

• Moe Marius
• Aaberge Tarjei
• Patel Bijit

Classifications

• H03K3/0315 Primary

  Ring oscillators · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title