Phase change memory using multiple phase change layers and multiple heat conductors

Patent metadata

Field	Value
Publication number	US-12310264-B2
Application number	US-202117548745-A
Country	US
Kind code	B2
Filing date	Dec 13, 2021
Priority date	Jun 12, 2019
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

First claim

The invention claimed is:

1. A semiconductor structure for reducing a reset current for a phase change memory (PCM), the semiconductor structure comprising:
a bottom electrode;
a PCM cell structure disposed over the bottom electrode, the PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, the heat transfer layers being metal liners, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, the plurality of phase change memory layers having different parallel lengths and an entirety of the phase change memory layers being perpendicular to a top surface of the bottom electrode; and
a top electrode disposed over the PCM cell structure.

2. The semiconductor structure of claim 1 , wherein the plurality of phase change memory layers each include a Ge—Sb—Te (germanium-antimony-tellurium or “GST”) alloy.

3. The semiconductor structure of claim 1 , wherein airgaps are defined adjacent the PCM cell structure.

4. The semiconductor structure of claim 3 , wherein the airgaps extend from the top electrode to the bottom electrode.

5. The semiconductor structure of claim 1 , wherein the PCM cell structure defines a U-shaped configuration.

6. The semiconductor structure of claim 5 , wherein an oxide material is disposed within the U-shaped configuration.

7. The semiconductor structure of claim 6 , wherein a pair of phase change memory layers are formed on one side of the oxide material and another pair of phase change memory layers are formed on an opposed side of the oxide material.

8. The semiconductor structure of claim 1 , wherein the plurality of heat transfer layers directly contact a top surface of the bottom electrode.

9. The semiconductor structure of claim 1 , wherein a first heat transfer layer of the plurality of heat transfer layers is in direct contact with a second heat transfer layer of the plurality of heat transfer layers and one of the plurality of phase change memory layers is arranged between the first and second heat transfer layers.

10. The semiconductor structure of claim 1 , wherein the plurality of phase change memory layers are disposed in a straight line when viewed in a cross-section.

Assignees

• IBM

Inventors

• Ok Injo
• Pranatharthiharan Balasubramanian
• Brew Kevin W
• Wang Wei

Classifications

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/8613

  Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title