Silicon carbide semiconductor device, power conversion apparatus, and method for manufacturing silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-12310076-B2
Application number	US-201917777070-A
Country	US
Kind code	B2
Filing date	Nov 28, 2019
Priority date	Nov 28, 2019
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A silicon carbide semiconductor device includes: a body region of a second conductivity type provided on a drift layer of a first conductivity type; a source region of a first conductivity type provided on the body region; a source electrode connected to the source region; a gate insulating film provided on an inner surface of a trench; a gate electrode provided inside the trench with interposition of the gate insulating film; a protective layer of a second conductivity type provided below the gate insulating film; a connection layer of a second conductivity type being in contact with the protective layer and the body region; and an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device comprising:
a substrate of a first conductivity type;
a drift layer of a first conductivity type made of silicon carbide provided on the substrate;
a body region of a second conductivity type provided on the drift layer;
a source region of a first conductivity type provided on the body region;
a source electrode connected to the source region;
a gate insulating film provided on an inner surface of a trench, the trench penetrating the body region and the source region and having a bottom surface positioned inside the drift layer;
a gate electrode provided inside the trench with interposition of the gate insulating film;
a protective layer of a second conductivity type provided below the gate insulating film;
a connection layer of a second conductivity type provided inside the drift layer and being in contact with the protective layer and the body region; and
an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

2. The silicon carbide semiconductor device according to claim 1 , wherein an impurity concentration of a second conductivity type of the electric field relaxation layer is lower than an impurity concentration of a second conductivity type of the protective layer.

3. The silicon carbide semiconductor device according to claim 1 , wherein the protective layer includes:
a high-concentration protective layer provided on a bottom surface side of the trench and having a higher impurity concentration of a second conductivity type than the body region, and
a low-concentration protective layer provided in contact with below the high-concentration protective layer and having a lower impurity concentration of a second conductivity type than the high-concentration protective layer.

4. The silicon carbide semiconductor device according to claim 1 , further comprising a low resistance layer of a first conductivity type provided in contact with a side surface of the connection layer and having a higher impurity concentration of a first conductivity type than the drift layer.

5. The silicon carbide semiconductor device according to claim 1 , wherein the electric field relaxation layer is in contact with a bottom surface of the protective layer.

6. The silicon carbide semiconductor device according to claim 1 ,
wherein the connection layer includes the connection layers, and the connection layers are provided so as to face each other with interposition of the trench, and
wherein the electric field relaxation layers are provided so as to be in contact with bottom surfaces of the connection layers facing each other with interposition of the trench, and a bottom surface of the protective layer, and be connected below the protective layer.

7. The silicon carbide semiconductor device according to claim 1 , wherein a width of the electric field relaxation layer is equal to or less than a width of the connection layer.

8. The silicon carbide semiconductor device according to claim 1 , wherein the drift layer includes two layers, a first drift layer and a second drift layer.

9. A power conversion apparatus comprising:
a main conversion circuit including the silicon carbide semiconductor device according to claim 1 and configured to convert input power and output converted power;
a drive circuit configured to output a drive signal to the silicon carbide semiconductor device; and
a control circuit configured to output a control signal to the drive circuit.

10. The silicon carbide semiconductor device according to claim 1 , wherein a side surface of the connection layer directly contacts a side surface of the protective layer.

11. A method for manufacturing a silicon carbide semiconductor device, the method comprising:
forming a semiconductor layer of a first conductivity type made of silicon carbide on a substrate;
forming a body region of a second conductivity type in an upper part inside the semiconductor layer;
forming a source region of a first conductivity type on a front surface of the body region;
forming a trench penetrating the body region from a front surface of the source region;
forming a gate insulating film on an inner surface of the trench;
forming a gate electrode inside the trench with interposition of the gate insulating film;
forming a protective layer of a second conductivity type below the gate insulating film;
forming an electric field relaxation layer of a second conductivity type by slantingly implanting ions into a region lateral to the protective layer; and
forming a connection layer of a second conductivity type having a higher impurity concentration of a second conductivity type than the electric field relaxation layer by slantingly implanting ions into a region above the electric field relaxation layer.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 11 ,
wherein the connection layer is formed by slanted ion implantation with a slant of an angle θ 1 from a direction perpendicular to a front surface of the source region,
wherein the electric field relaxation layer is formed by slanted ion implantation with a slant of an angle θ 2 from a direction perpendicular to a front surface of the source region, and
wherein the angle θ 1 is larger than the angle θ 2 .

13. A method for manufacturing a silicon carbide semiconductor device, the method comprising:
forming a first drift layer of a first conductivity type made of silicon carbide on a substrate;
forming an electric field relaxation layer of a second conductivity type inside the first drift layer;
forming one part of a connection layer of a second conductivity type having a higher impurity concentration of a second conductivity type than the electric field relaxing layer so as to be in contact with a front surface of the electric field relaxing layer in an upper part inside the first drift layer;
forming a protective layer in a part of a region where the electric field relaxation layer and the connection layer are formed;
forming a second drift layer of a first conductivity type on the first drift layer by epitaxial crystal growth;
forming a body region of a second conductivity type in an upper part inside the second drift layer;
forming a source region of a first conductivity type on a front surface of the body region;
forming a trench penetrating the body region from a front surface of the source region;
forming another part of the connection layer inside the second drift layer so as to be in contact with the one part of the connection layer on a front surface side;
forming a gate insulating film on an inner surface of the trench; and
forming a gate electrode inside the trench with interposition of the gate insulating film.

Assignees

• Mitsubishi Electric Corp

Inventors

• Tanaka Rina
• Fukui Yutaka
• Hatta Hideyuki
• Adachi Kohei

Classifications

• H10P30/22

  using masks · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H02M7/53871

  with automatic control of output voltage or current · CPC title