Decoupling capacitors and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12310001-B2
Application number	US-202117358930-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

First claim

What is claimed is:

1. A device structure comprising:
a plurality of transistors laterally spaced apart along a first direction on a first level in a first region;
a first plurality of capacitors on a second level, above the first level, wherein a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor in the plurality of transistors; and
a second plurality of capacitors laterally spaced apart along the first direction on the second level in a second region adjacent to the first region, wherein individual ones of the second plurality of capacitors comprise:
a second electrode, a third electrode, and an insulator layer therebetween, wherein the second electrode of the individual ones of the second plurality of capacitors are coupled with a first interconnect on a third level above the second level, a first conductive plate couples the first interconnect and divides the first interconnect into first and second portions, the first portion above the first conductive plate, the first conductive plate above the second portion, the third electrode of the individual ones of the second plurality of capacitors are coupled with a second interconnect, and a second conductive plate couples the second interconnect and divides the second interconnect into third and fourth portions, the third portion above the second conductive plate, the second conductive plate above the fourth portion.

2. The device structure of claim 1 , wherein the first conductive plate is above the respective second electrodes, the first interconnect is a first via, the first conductive plate laterally extending to the first via, and the first and second portions are vertical portions of the first via.

3. The device structure of claim 2 , wherein the second conductive plate is below the respective third electrodes, the second interconnect is a second via, the second conductive plate laterally extending to the second via, and the third and fourth portions are vertical portions of the second via.

4. The device structure of claim 2 , wherein the insulator layer is a first insulator layer, and wherein the first conductive plate laterally extends over a third plurality of capacitors laterally spaced apart along a direction parallel to the first direction, wherein individual ones of the third plurality of capacitors comprise a fourth electrode, a fifth electrode, and an second insulator layer therebetween, and wherein the fourth electrode of the individual ones of the third plurality of capacitors are coupled with the first conductive plate.

5. The device structure of claim 4 , wherein the second conductive plate laterally extends under the third plurality of capacitors and couples with the fifth electrode of the individual ones of the third plurality of capacitors.

6. The device structure of claim 1 , wherein the device structure is coupled with a motherboard.

7. The device structure of claim 1 , wherein the first plurality of capacitors has a first width and a first height, and the second plurality of capacitors has the first width and the first height.

8. The device structure of claim 1 , wherein the individual ones of the second plurality of capacitors have a lateral width that is up to three time greater than a lateral width of the individual ones of the first plurality of capacitors.

9. The device structure of claim 1 , wherein the device structure further comprises:
a first word line on a fourth level below the first level in the first region, the first word line coupled with a gate electrode of a respective transistor in the plurality of transistors;
a second word line on the fourth level in the second region; and
a plurality of vias on and in contact with an uppermost surface of the second word line, wherein individual ones of the plurality of vias are further coupled with a respective third electrode of the individual ones of the second plurality of capacitors.

10. The device structure of claim 9 , wherein the insulator layer is a first insulator layer and the plurality of vias is a first plurality of vias, and wherein the device structure further comprises:
a fourth plurality of capacitors on the second level in the second region, wherein the fourth plurality of capacitors comprise a sixth electrode, a seventh electrode, and a third insulator layer there between;
a third word line on the fourth level in the second region, the third word line parallel to the second word line; and
a second plurality of vias on and in contact with an uppermost surface of the third word line, wherein individual ones of the second plurality of vias are further coupled with a respective seventh electrode of the individual ones of the fourth plurality of capacitors.

11. A device structure comprising:
a first plurality of transistors on a first level in a first region;
a first plurality of capacitors on a second level, above the first level, wherein individual ones of a first electrode of the first plurality of capacitors are coupled with a terminal of a respective transistor in the first plurality of transistors, and wherein individual ones of a second electrode of the first plurality of capacitors are coupled with a first interconnect;
a first word line coupled with a respective gate of the first plurality of transistors;
a second plurality of transistors on the first level in a second region, adjacent the first region, wherein individual ones of the second plurality of transistors comprise:
a respective gate electrode;
a first terminal; and
a second terminal;

a second plurality of capacitors on the second level, wherein individual ones of the second plurality of capacitors comprise respective first and second electrodes, individual ones of the first electrodes of the second plurality of capacitors are coupled with the first terminal of a respective transistor in the second plurality of transistors, individual ones of the second electrodes of the second plurality of capacitors are coupled with a second interconnect, and the second terminal of the individual ones of the second plurality of transistors are coupled with each other through a third interconnect; and
a second word line coupled with a respective gate electrode of the first-second plurality of transistors.

12. The device structure of claim 11 , wherein the second electrodes of the individual ones of the second plurality of capacitors are coupled together by a conductive plate laterally extending to the first interconnect.

13. The device structure of claim 12 , wherein the first interconnect is a via and wherein the conductive plate divides the via into two vertical portions.

14. The device structure of claim 13 , wherein the second terminal of the individual ones of the second plurality of transistors are coupled with a respective metallization interconnect that extend in a direction that is orthogonal to a longitudinal direction of the second word line, and wherein the respective metallization interconnect couples with the third interconnect.

15. The device structure of claim 11 , further comprising a third word line parallel to the second word line, wherein the third word line further comprises:
a third plurality of transistors on the first level in the second region, wherein individual ones of third plurality of transistors comprise:
a respective gate electrode;
a respective first terminal; and
a respective second terminal; and

a third plurality of capacitors on the second level, wherein individual ones of the third plurality of capacitors comprise respective first and second electrodes, individual ones of the first electrodes of the

Assignees

• Intel Corp

Inventors

• Alzate-Vinasco Juan G
• Lajoie Travis W
• Gomes Wilfred
• Hamzaoglu Fatih
• Jain Pulkit
• Waldemer James
• Armstrong Mark
• Sell Bernhard
• Wang Pei-Hua
• Ku Chieh-Jen

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/05

  Making the transistor · CPC title