Wiring substrate

Patent metadata

Field	Value
Publication number	US-12309920-B2
Application number	US-202218062049-A
Country	US
Kind code	B2
Filing date	Dec 6, 2022
Priority date	Dec 6, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A wiring substrate includes an insulating layer including inorganic filler particles and resin, and a conductor layer including a metal film formed on a surface of the insulating layer and having a conductor pattern. The inorganic filler particles include first inorganic filler particles such that each of the first inorganic filler particles has a portion exposed on the surface of the insulating layer and is at least partially separated from the resin, the conductor layer is formed such that a part of the metal film is between the first inorganic filler particles and the resin from the surface of the insulating layer and that a distance between the surface of the insulating layer and the surface of the insulating layer at a deepest part of the part of the metal film is in the range of 0.1 μm to 0.5 μm.

First claim

The invention claimed is:

1. A wiring substrate, comprising:
an insulating layer comprising inorganic filler particles and resin; and
a conductor layer comprising a metal film formed on a surface of the insulating layer and having a conductor pattern,
wherein the inorganic filler particles include first inorganic filler particles such that each of the first inorganic filler particles has an exposed portion exposed from the surface of the insulating layer and is at least partially separated from the resin, and the conductor layer is formed such that a part of the metal film is penetrating in a gap or gaps formed between the exposed portion of each of the first inorganic filler particles and the resin forming the surface of the insulating layer and that a distance between the surface of the insulating layer and the surface of the insulating layer at a deepest part of the part of the metal film is in a range of 0.1 μm to 0.5 μm.

2. The wiring substrate according to claim 1 , wherein the insulating layer is formed such that the surface of the insulating layer includes a region in which 5 or more of the first inorganic filler particles exist per 10 μm.

3. The wiring substrate according to claim 1 , wherein the conductor layer has a plurality of wiring patterns having a minimum wiring interval in a range of 3 μm to 15 μm.

4. The wiring substrate according to claim 3 , wherein the conductor layer is formed such that a minimum wiring width of the wiring patterns is in a range of 3 μm to 15 μm.

5. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the metal film is an electroless plating film.

6. The wiring substrate according to claim 1 , wherein the insulating layer is formed such that a content rate of the inorganic filler particles in the insulating layer is in a range of 65% to 80%.

7. The wiring substrate according to claim 1 , wherein the insulating layer has recesses on the surface of the insulating layer and is formed such that the first inorganic filler particles are partially formed in the recesses on the surface of the insulating layer and that the part of the metal film is in deepest parts of the recesses.

8. The wiring substrate according to claim 1 , wherein the insulating layer is formed such that the surface of the insulating layer has an arithmetic mean roughness in a range of 0.05 μm to 0.5 μm.

9. The wiring substrate according to claim 2 , wherein the conductor layer has a plurality of wiring patterns having a minimum wiring interval in a range of 3 μm to 15 μm.

10. The wiring substrate according to claim 9 , wherein the conductor layer is formed such that a minimum wiring width of the wiring patterns is in a range of 3 μm to 15 μm.

11. The wiring substrate according to claim 2 , wherein the conductor layer is formed such that the metal film is an electroless plating film.

12. The wiring substrate according to claim 2 , wherein the insulating layer is formed such that a content rate of the inorganic filler particles in the insulating layer is in a range of 65% to 80%.

13. The wiring substrate according to claim 2 , wherein the insulating layer has recesses on the surface of the insulating layer and is formed such that the first inorganic filler particles are partially formed in the recesses on the surface of the insulating layer and that the part of the metal film is in deepest parts of the recesses.

14. The wiring substrate according to claim 2 , wherein the insulating layer is formed such that the surface of the insulating layer has an arithmetic mean roughness in a range of 0.05 μm to 0.5 μm.

15. The wiring substrate according to claim 3 , wherein the conductor layer is formed such that the metal film is an electroless plating film.

16. The wiring substrate according to claim 3 , wherein the insulating layer is formed such that a content rate of the inorganic filler particles in the insulating layer is in a range of 65% to 80%.

17. The wiring substrate according to claim 3 , wherein the insulating layer has recesses on the surface of the insulating layer and is formed such that the first inorganic filler particles are partially formed in the recesses on the surface of the insulating layer and that the part of the metal film is in deepest parts of the recesses.

18. The wiring substrate according to claim 3 , wherein the insulating layer is formed such that the surface of the insulating layer has an arithmetic mean roughness in a range of 0.05 μm to 0.5 μm.

19. The wiring substrate according to claim 4 , wherein the insulating layer is formed such that a content rate of the inorganic filler particles in the insulating layer is in a range of 65% to 80%.

20. The wiring substrate according to claim 4 , wherein the insulating layer has recesses on the surface of the insulating layer and is formed such that the first inorganic filler particles are partially formed in the recesses on the surface of the insulating layer and that the part of the metal film is in deepest parts of the recesses.

Assignees

• Ibiden Co Ltd

Inventors

• Fukui Shogo
• Ikeda Kosuke
• Ichikawa Kosei
• Ando Ryo

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H05K1/112

  directly combined with via connections · CPC title

• H05K2201/0209

  Inorganic, non-metallic particles · CPC title