Hardware queue scheduling for multi-core computing environments

Patent metadata

Field	Value
Publication number	US-12309067-B2
Application number	US-202017637416-A
Country	US
Kind code	B2
Filing date	Sep 11, 2020
Priority date	Sep 11, 2019
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

First claim

What is claimed is:

1. An apparatus for hardware queue scheduling in a multi-core computing environment, the apparatus comprising:
a first core and a second core of a processor; and
circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to:
enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet;
assign the identifier in the queue to a first core of the processor; and
after obtaining a notification that an execution of an operation on the data packet with the first core has completed, provide the identifier to the second core to cause the second core to distribute the data packet.

2. The apparatus of claim 1 , wherein the queue is a first queue, and the circuitry is to:
determine a priority of the identifier based on the identifier;
dequeue the identifier from the first queue to first arbitration circuitry, the first arbitration circuitry associated with the priority;
provide the identifier from the first arbitration circuitry to second arbitration circuitry, the second arbitration circuitry associated with the first core; and
enqueue the identifier from the second arbitration circuitry to a second queue, the second queue associated with the first core, the first core to dequeue the identifier from the second queue.

3. The apparatus of claim 1 , wherein the identifier is a first identifier, the operation is a first operation, and the circuitry is to:
assign a second identifier in the queue to a third core of the processor based on a throughput parameter not satisfying a throughput threshold, the throughput parameter based on telemetry data obtained from at least one of the first core or the second core, the second identifier associated with a second data packet; and
based on the third core executing a second operation on the second data packet, provide the second identifier to the second core or a fourth core of the processor to cause the second core or the fourth core to distribute the second data packet.

4. The apparatus of claim 1 , wherein the queue is a first queue, and the circuitry is to:
receive, at a port of the circuitry, the identifier;
execute, with reordering logic circuitry, a reordering operation on the identifier;
identify, with arbitration logic circuitry, a second queue to store the identifier; and
enqueue the identifier to the second queue, the first core to dequeue the identifier from the second queue.

5. The apparatus of claim 4 , wherein the identifier is a first identifier, the data packet is a first data packet, and the circuitry is to:
cause storage of the first identifier in an order buffer;
determine whether a second identifier is stored in the order buffer, the second identifier associated with a second data packet to be distributed after the first data packet;
after determining that the second identifier is stored in the order buffer, enqueue the first identifier in the queue; and
after enqueuing the first identifier in the queue, enqueue the second identifier in the queue.

6. The apparatus of claim 1 , wherein:
the first core is to:
provide the notification of the completion of the operation to the circuitry; and
cause storage of the data packet in memory; and

the second core is to retrieve the data packet from the memory after the circuitry provides the identifier to the second core.

7. The apparatus of claim 1 , wherein the circuitry is to:
identify a data source of the identifier;
determine whether the data source has a producer credit, the identifier enqueued to the queue after determining that the data source has the producer credit;
deduct the producer credit from a number of producer credits associated with the data source, the number of producer credits stored in memory; and
after a distribution of the data packet, add the producer credit to the number of the producer credits.

8. An apparatus for hardware queue scheduling in a multi-core computing environment, the apparatus comprising:
means for enqueuing an identifier to a queue, the queue implemented with circuitry in a die of a processor, the identifier associated with a data packet;
means for assigning the identifier in the queue to a first core of the processor; and
means for allocating the identifier to a second core to cause the second core to distribute the data packet, the means for allocating to allocate the identifier to the second core after obtaining a notification that an execution of an operation on the data packet with the first core has completed, at least one of the first core or the second core are included in the die of the processor, the at least one of the first core or the second core separate from the circuitry.

9. The apparatus of claim 8 , wherein the queue is a first queue, and including arbitration means to:
determine a priority of the identifier based on the identifier;
dequeue the identifier from the first queue to first arbitration logic, the first arbitration logic associated with the priority;
provide the identifier from the first arbitration logic to second arbitration logic, the second arbitration logic associated with the first core; and
enqueue the identifier from the second arbitration logic to a second queue, the second queue associated with the first core, the first core to dequeue the identifier from the second queue.

10. The apparatus of claim 8 , wherein the identifier is a first identifier, the operation is a first operation, and:
the means for assigning is to assign a second identifier in the queue to a third core of the processor based on a throughput parameter not satisfying a throughput threshold, the throughput parameter based on telemetry data obtained from at least one of the first core or the second core, the second identifier associated with a second data packet; and
the means for allocating is to allocate the second identifier to the second core or a fourth core of the processor to cause the second core or the fourth core to distribute the second data packet.

11. The apparatus of claim 8 , wherein the queue is a first queue, and including:
means for receiving the identifier; and
means for executing a reordering operation on the identifier; and
the means for assigning is to identify a second queue to enqueue the identifier; and
the means for allocating is to enqueue the identifier to the second queue, the first core to dequeue the identifier from the second queue.

12. The apparatus of claim 11 , wherein the identifier is a first identifier, the data packet is a first data packet, and:
the means for executing is to:
cause storage of the first identifier in an order buffer; and
determine whether a second identifier is stored in the order buffer, the second identifier associated with a second data packet to be distributed after the first data packet; and

the means for enqueuing is to:
enqueue the first identifier in the queue after determining that the second identifier is stored in the order buffer; and
enqueue the second identifier in the queue after enqueuing the first identifier in the queue.

13. The apparatus of claim 8 , further including:
means for obtaining a notification of a completion of the operation from the first core, the first core to store the data packet in memory; and
the means for allocating is to allocate the identifier to the second core, the second core to retrieve the data packet from the memory after receiving the identifier.

14. The apparatus of claim 8 , including means for managing a number of

Assignees

• Intel Corp

Inventors

• Mcdonnell Niall
• Eads Gage
• Ganguli Mrittika
• Hiremath Chetan
• Mangan John
• Palermo Stephen
• Richardson Bruce
• Verplanke Edwin
• Mosur Praveen
• Chaddick Bradley
• Khade Abhishek
• Layek Abhirupa
• Maini Sarita
• Shah Rahul
• Shah Shrikant
• Burroughs William
• Sonnier David

Classifications

• H04L47/6275

  based on priority · CPC title

• H04L47/6255

  queue load conditions, e.g. longest queue first · CPC title

• H04L47/624

  Altering the ordering of packets in an individual queue · CPC title

• H04L47/62

  characterised by scheduling criteria · CPC title

• H04L47/125 Primary

  by balancing the load, e.g. traffic engineering · CPC title