Amplifier circuit

Patent metadata

Field	Value
Publication number	US-12308868-B2
Application number	US-202218550781-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

An amplifier circuit includes: an amplifier connected to an isolating element; a signal midpoint detecting circuit connected in parallel with the isolating element; a bias adding circuit connected in series with the signal midpoint detecting circuit; and an initial voltage value detecting circuit connected to the frame detecting circuit. The initial voltage value detecting circuit holds an initial voltage value of the baseband signal using a signal from the frame detecting circuit, and outputs the initial voltage value to the signal midpoint detecting circuit. The signal midpoint detecting circuit detects a midpoint voltage from the baseband signal and the initial voltage value, and outputs the midpoint voltage to the bias adding circuit. The bias adding circuit adds the midpoint voltage to a bias voltage for biasing the baseband signal. The amplifier amplifies the baseband signal.

First claim

The invention claimed is:

1. An amplifier circuit, comprising:
an isolating element connected to an input terminal;
an amplifier connected between the isolating element and an output terminal;
a signal midpoint detecting circuit connected in parallel to the isolating element;
a bias adding circuit connected in series with the signal midpoint detecting circuit; and
an initial voltage value detecting circuit connected to a frame detecting circuit;
wherein the initial voltage value detecting circuit is configured to hold an initial voltage value of one of a plurality of baseband signals and output the initial voltage value to the signal midpoint detecting circuit, the plurality of baseband signals being input to the amplifier circuit from a preceding amplifier circuit in a preceding stage;
wherein the signal midpoint detecting circuit is configured to detect a midpoint voltage from the plurality of baseband signals and the initial voltage value, and output the midpoint voltage to the bias adding circuit;
wherein the bias adding circuit is configured to add the midpoint voltage to a bias voltage for biasing the plurality of baseband signals; and
wherein the amplifier is configured to amplify the plurality of baseband signals.

2. The amplifier circuit according to claim 1 , wherein an output of the amplifier is input to the frame detecting circuit.

3. The amplifier circuit according to claim 1 , wherein:
the initial voltage value detecting circuit comprises a signal delaying circuit connected to the input terminal, and a sample-and-hold circuit connected to the signal delaying circuit;
the signal midpoint detecting circuit comprises a low pass filter connected to the input terminal, and a midpoint voltage calculating circuit connected to the low pass filter;
the sample-and-hold circuit is configured to hold an initial voltage value of the plurality of baseband signals input from the signal delaying circuit in accordance with a signal from the frame detecting circuit and output the initial voltage value to the midpoint voltage calculating circuit; and
the midpoint voltage calculating circuit is configured to output a difference between an output of the low pass filter and an output of the sample-and-hold circuit to the bias adding circuit.

4. The amplifier circuit according to claim 1 , wherein:
the amplifier circuit comprises a plurality of isolating elements, a plurality of signal midpoint detecting circuits, a plurality of bias adding circuits, and a plurality of amplifiers;
each of the plurality of signal midpoint detecting circuits is connected to a corresponding one of the plurality of isolating elements in parallel thereto;
the initial voltage value detecting circuit is configured to output to a corresponding one of the plurality of signal midpoint detecting circuits; and
each of the plurality of signal midpoint detecting circuits is configured to output to a corresponding one of the plurality of bias adding circuits.

5. An amplifier circuit, comprising:
a plurality of isolating elements each connected to a corresponding one of a plurality of input terminals;
a plurality of amplifiers each connected between a corresponding one of the plurality of isolating elements and a corresponding one of a plurality of output terminals;
a plurality of signal midpoint detecting circuits each connected in parallel to a corresponding one of the plurality of isolating elements;
a plurality of bias adding circuits each connected in series with a corresponding one of the plurality of signal midpoint detecting circuits; and
an inter-channel interpolating low voltage (VL) detecting circuit;
wherein the inter-channel interpolating VL detecting circuit is configured to detect a low voltage signal among a plurality of baseband signals and outputs the low voltage signal to the corresponding one of the plurality of signal midpoint detecting circuits, wherein the plurality of baseband signals is input from a plurality of preceding amplifier circuits in a preceding stage of the amplifier circuit;
wherein the plurality of signal midpoint detecting circuits is configured to detect a midpoint voltage from the plurality of baseband signals and the low voltage signal and outputs the midpoint voltage to a corresponding one of the plurality of bias circuits;
wherein the plurality of bias adding circuits is configured to add the midpoint voltage to a bias voltage for biasing the plurality of baseband signals; and
wherein the plurality of amplifiers is configured to amplify the plurality of the baseband signals.

6. The amplifier circuit according to claim 5 , wherein:
the inter-channel interpolating VL detecting circuit comprises a plurality of diode circuits, a resistor, and a voltage source;
each of the plurality of baseband signals is input to a first end of each of the plurality of diode circuits;
the voltage source is connected to a second end of each of the plurality of diode circuits via the resistor; and
the diode circuit is connected such that a direction from the second end to the first end is in a forward direction.

7. A connection circuit connected to preceding stages in a plurality of transmitter circuits and to which a plurality of baseband signals are input, the connection circuit comprising:
a plurality of isolating elements each connected between a corresponding one of a plurality of input terminals and a corresponding one of a plurality of output terminals;
a plurality of amplifiers each connected between a corresponding one of the plurality of isolating elements and the corresponding one of the plurality of output terminals;
a plurality of frame detecting circuits each connected in parallel to the corresponding one of the plurality of isolating elements;
a plurality of switching devices each connected in series with a corresponding one of the plurality of frame detecting circuits;
a plurality of bias adding circuits each connected in series with a corresponding one of the plurality of switching devices; and
a differential mean midpoint voltage calculating circuit to which an output of an inter-channel interpolating low voltage (VL) detecting circuit and an output of an inter-channel interpolating high voltage (VH) detecting circuit are input;
wherein the inter-channel interpolating VL detecting circuit is configured to detect an input of a low voltage signal in the plurality of baseband signals and outputs the low voltage signal to the differential mean midpoint voltage calculating circuit;
wherein the inter-channel interpolating VH detecting circuit is configured to detect an input of a high voltage signal in the plurality of baseband signals and outputs the high voltage signal to the differential mean midpoint voltage calculating circuit;
wherein the differential mean midpoint voltage calculating circuit is configured to output a midpoint voltage to the plurality of switching devices from an output of the inter-channel interpolating VL detecting circuit and an output of the inter-channel interpolating VH detecting circuit; wherein each of the plurality of switching devices is configured to output the midpoint voltage to a corresponding one of the plurality of bias adding circuits in accordance with an input from the corresponding one of the plurality of the frame detecting circuits; wherein each of the bias adding circuits is configured to add the midpoint voltage to a corresponding bias voltage for biasing a corresponding one of the plurality of baseband signals; and wherein each of the plurality of amplifiers is configured to amplify the corresponding one of the plurality of baseband signals.

8. The connection circuit according to claim 7 , wherein:
the inter-channel interpolating VH detecting circuit comprises a pluralit

Assignees

• Nippon Telegraph & Telephone
• Ntt Innovative Devices Corp

Inventors

• Minotani Tadashi
• Kishi Toshiki
• Tobayashi Masatoshi
• Urabe Yoshikazu

Classifications

• H03F3/19

  with semiconductor devices only · CPC title

• H03F1/0272

  by using a signal derived from the output signal · CPC title

• H03F1/0266

  by using a signal derived from the input signal · CPC title

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title