Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof

Patent metadata

Field	Value
Publication number	US-12308316-B2
Application number	US-202217712067-A
Country	US
Kind code	B2
Filing date	Apr 2, 2022
Priority date	Dec 23, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Embodiments provide an anti-fuse storage layout and a circuit thereof, and an anti-fuse memory and a design method thereof. The anti-fuse storage layout includes: active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions including at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions including an anti-fuse region and a control region arranged along the first direction, and the control regions of the adjacent memory cell regions being adjacent to each other along the first direction; a word line region extending along the second direction and intersecting with the control region; an electrical connection region extending along the second direction and intersecting with the anti-fuse region; and a programming control region extending along a third direction and being positioned at one side of the corresponding active region.

First claim

What is claimed is:

1. An anti-fuse storage layout, comprising:
active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions comprising at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions comprising an anti-fuse region and a control region arranged along the first direction, the control regions of the adjacent memory cell regions being adjacent to each other along the first direction, the anti-fuse region being configured to define an anti-fuse transistor, and the control region being configured to define a control transistor;
a word line region extending along the second direction and intersecting with the control region, the word line region being configured to define a word line electrically connected to a gate of the control transistor;
an electrical connection region extending along the second direction and intersecting with the anti-fuse region, the electrical connection region being configured to define an electrical connection layer electrically connected to a gate of the anti-fuse transistor; and
a programming control region extending along a third direction and being positioned at one side of the corresponding active region, the programming control region intersecting with the electrical connection region arranged along the first direction, the programming control region being configured to define a programming control layer, and the programming control layer being electrically connected to the electrical connection layer arranged along the first direction.

2. The anti-fuse storage layout according to claim 1 , wherein the programming control region and the electrical connection region are in the same layer, the programming control region and the electrical connection region being adjacent to each other.

3. The anti-fuse storage layout according to claim 1 , wherein the programming control region and the electrical connection region are in different layers, the programming control region and the electrical connection region having a facing region.

4. The anti-fuse storage layout according to claim 3 , wherein the anti-fuse storage layout further comprises:
a through-hole region positioned in the facing region between the programming control region and the electrical connection region, the through-hole region being configured to define a conductive pillar, and the conductive pillar being electrically connected to the electrical connection layer and the programming control layer.

5. The anti-fuse storage layout according to claim 1 , wherein the first direction is the same as the third direction.

6. The anti-fuse storage layout according to claim 1 , wherein the first direction is perpendicular to the second direction.

7. The anti-fuse storage layout according to claim 1 , wherein the active region is configured to define an N-type active layer.

8. The anti-fuse storage layout according to claim 1 , further comprising:
a bit line region extending along the first direction, the bit line region being configured to define a bit line electrically connected to the control transistor arranged along the first direction.

9. An anti-fuse memory, comprising:
at least two memory cells arranged along a first direction and a second direction, each of the at least two memory cells comprising an anti-fuse transistor and a control transistor arranged along the first direction, a gate structure of the anti-fuse transistor comprising a first gate dielectric layer and a first gate layer arranged in a stack, and a gate structure of the control transistor comprising a second gate dielectric layer and a second gate layer arranged in a stack;
a word line layer, the word line layer extending along the second direction and being electrically connected to the first gate layer of the control transistor arranged along the second direction;
an electrical connection layer, the electrical connection layer extending along the second direction and being electrically connected to the second gate layer of the anti-fuse transistor; and
a programming control layer, the programming control layer extending along a third direction and being electrically connected to the first gate layer arranged along the first direction by means of the electrical connection layer.

10. The anti-fuse memory according to claim 9 , wherein the electrical connection layer and the programming control layer are in the same layer.

11. The anti-fuse memory according to claim 9 , wherein the electrical connection layer and the programming control layer are in different layers; the anti-fuse memory further comprising:
a conductive pillar, the conductive pillar being positioned between the electrical connection layer and the programming control layer, and being electrically connected to the electrical connection layer and the programming control layer.

12. The anti-fuse memory according to claim 9 , wherein a thickness of the first gate dielectric layer is less than or equal to 30 angstroms, a thickness of the second gate dielectric layer being less than or equal to 30 angstroms.

13. The anti-fuse memory according to claim 9 , further comprising: a bit line layer extending along the first direction, wherein the bit line layer is electrically connected to the control transistor arranged along the first direction.

14. An anti-fuse storage circuit, comprising:
a plurality of memory cells, each of the plurality of memory cells comprising an anti-fuse transistor and a control transistor connected to each other, and a connection node between the anti-fuse transistor and the control transistor being defined as a reference node;
a bit line connected to the anti-fuse transistors arranged along a first direction, each of the anti-fuse transistors being electrically connected to the bit line by means of the control transistor;
a word line connected to a gate of the control transistor arranged in a second direction, the word line being configured to enable the selected control transistor according to a row strobe signal, such that the bit line is electrically connected to the anti-fuse transistor; and
a programming control line connected to a gate of the anti-fuse transistor arranged along the first direction, the anti-fuse transistor being configured to programme according to a programming signal provided by the programming control line;
wherein there is a first parasitic capacitance between the gate of the anti-fuse transistor and the reference node, and there being a second parasitic capacitance between the gate of the control transistor and the reference node, during programming by means of the anti-fuse transistor of a selected one of the plurality of memory cells, the reference nodes of the adjacent anti-fuse transistors being coupled to a preset voltage, and a difference value between the preset voltage and a voltage of the programming signal being less than or equal to a voltage difference threshold, and the voltage difference threshold being a voltage difference between the gate and a drain corresponding to breakdown of the anti-fuse transistor.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10B20/20

  Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) · CPC title

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title