Reconfigurable MBIST method based on adaptive march algorithm

Patent metadata

Field	Value
Publication number	US-12308085-B2
Application number	US-202318277382-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Aug 19, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A reconfigurable MBIST method based on an adaptive March algorithm is provided. The reconfigurable MBIST method automatically reconfigures different algorithm circuits according to external environment and user instructions to satisfy detection requirements for different faults. The provided adaptive March algorithm is capable of adaptively reorganizing algorithms with different complexities, such that dynamic adjustments can be executed between time complexities of the algorithm and fault coverage rates to achieve a good balance, and the static fault coverage rates are high, thereby effectively improving dynamic fault coverage rates.

First claim

What is claimed is:

1. A reconfigurable MBIST method based on an adaptive March algorithm, comprising:
inserting, after a first read operation of testing steps for sequentially reading and writing storage units in a classic March C+ testing algorithm, Hammer testing algorithm elements which are defined as {↓(w0,r0 n ,r0); ↓(w1,r1 n ,r1)}, where ↓(w0,r0 n ,r0) represents an execution of operations on writing 0, reading 0 n times, reading 0 for the storage units in a memory according to a descending order of addresses, ↓(w1,r1 n ,r1) represents an execution of operations on writing 1, reading 1 n times, reading 1 for the storage units in the memory according to the descending order of the addresses, and a set value for n is configured according to user-defined instructions;
determining, by comparing PVT parameters with a fault model library, fault prone types under current PVT parameters, selecting a March algorithm that covers the fault prone types under the current PVT parameters, and generating algorithm element selection signals for reconfiguring the March algorithm;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w1,r1); ↑(r1,w0,r0); ↓(r0,w1,r1); ↓(r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals merely select testing elements of the March C+ testing algorithm, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to an ascending order or the descending order of the addresses; ↑(r0,w1,r1) represents an execution of operations on reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w0,r0) represents an execution of operations on reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w1,r1) represents an execution of operations on reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w0,r0) represents an execution of operations on reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; and ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0,r0,w1,r1); ↑(r1,w1,r1,r1,w0,r0); ↓(r0,w0,r0,r0,w1,r1); ↓(r1,w1,r1,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements and the set value for n is 1, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; ↑(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; and
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0,r0,w1,r1); ↑(r1,w1,r1,r1,w0,r0); ↓(r0,w0,r0 n ,r0,w1,r1); ↓(r1,w1,r1 n ,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements and the set value for n is greater than 1, where ↑↓(w0) represents an execution of operations on writing 0 for the storage units in the memory according to the ascending order or the descending order of the addresses; ↑(r0,w0,r0,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0, reading 0, writing 1, reading 1 for the storage units in the memory according to the ascending order of the addresses; ↑(r1,w1,r1,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1, reading 1, writing 0, reading 0 for the storage units in the memory according to the ascending order of the addresses; ↓(r0,w0,r0 n ,r0,w1,r1) represents an execution of operations on reading 0, writing 0, reading 0 n times, reading 0, writing 1, reading 1 for the storage units in the memory according to the descending order of the addresses; ↓(r1,w1,r1 n ,r1,w0,r0) represents an execution of operations on reading 1, writing 1, reading 1 n times, reading 1, writing 0, reading 0 for the storage units in the memory according to the descending order of the addresses; ↑↓(r0) represents an execution of operations on reading 0 for the storage units in the memory according to the ascending order or the descending order of the addresses.

2. A reconfigurable MBIST method based on an adaptive March algorithm, comprising:
inserting, after a first read operation of testing steps for sequentially reading and writing storage units in a classic March C+ testing algorithm, Hammer testing algorithm elements which are defined as {↑(w0,r0 n ,r0); ↑(w1,r1 n ,r1)}, where ↑(w0,r0 n ,r0) represents an execution of operations on writing 0, reading 0 n times, reading 0 for the storage units in a memory according to an ascending order of addresses, ↑(w1,r1 n ,r1) represents an execution of operations on writing 1, reading 1 n times, reading 1 for the storage units in the memory according to the ascending order of the addresses, and a set value for n is configured according to user-defined instructions;
determining, by comparing PVT parameters with a fault model library, fault prone types under current PVT parameters, selecting a March algorithm that covers the fault prone types under the current PVT parameters, and generating algorithm element selection signals for reconfiguring the March algorithm;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w1,r1); ↑(r1,w0,r0); ↓(r0,w1,r1); ↓(r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals merely select testing elements of the March C+ testing algorithm;
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0,r0,w1,r1); ↑(r1,w1,r1,r1,w0,r0); ↓(r0,w0,r0,r0,w1,r1); ↓(r1,w1,r1,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements in each of the testing steps and the set value for n is 1; and
sequentially executing, by the reconfigurable MBIST method, test steps which are defined as {↑↓(w0); ↑(r0,w0,r0 n ,r0,w1,r1); ↑(r1,w1,r1 n ,r1,w0,r0); ↓(r0,w0,r0,r0,w1,r1); ↓(r1,w1,r1,r1,w0,r0); ↑↓(r0)}, in a case where the algorithm element selection signals select all testing elements in each of the testing steps and the set value for n is greater than 1.

3. A reconfigurable MBIST method based on an adaptive March algorithm, comprising:
inserting, after a first read operation of testing steps for sequentially reading and writing storage units in a classic March C+ testing algorithm, Hammer testing algorithm elements which are defined as {↓(w0,r0 n ,r0); ↓(w1,r1 n ,r1)}, and adding read and write operations at a front and a rear of the Ha

Assignees

• Univ Nanjing Posts & Telecommunications
• Nantong Institute Of Nanjing Univ Of Posts And Telecommunications Co Ltd

Inventors

• Cai Zhikuang
• Yu Haojie
• Shen Haijun
• Xie Zushuai
• Guo Jingjing
• Liu Lu
• Yao Jiafei
• Wang Henglu
• Wang Zixuan
• Xiao Jian
• Guo Yufeng

Classifications

• G11C2029/3602

  Pattern generator · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/54

  Arrangements for designing test circuits, e.g. design for test [DFT] tools · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title