Display substrate, method of manufacturing the same and display device

Patent metadata

Field	Value
Publication number	US-12307948-B2
Application number	US-202218027308-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 30, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A display substrate, a method of manufacturing the same and a display substrate. The display substrate includes a plurality of first gate driving circuits and a plurality of second gate driving circuits, a first gate driving signal output by the first gate driving circuit and a second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line.

First claim

What is claimed is:

1. A display substrate, comprising: a plurality of first gate driving circuits and a plurality of second gate driving circuits, wherein a first gate driving signal output by the first gate driving circuit and a second gate driving signal output by the second gate driving circuit have different timing; the first gate driving circuit and the second gate driving circuit share at least one signal line;
wherein the first gate driving circuit and the second gate driving circuit share a first level signal line, and the first level signal line transmits a DC signal having a first level;
wherein the first gate driving circuit and the second gate driving circuit share a first clock signal line and/or a second clock signal line, a phase of a first clock signal transmitted by the first clock signal line is opposite to a phase of a second clock signal transmitted by the second clock signal line;
wherein the first gate driving circuit is coupled to a first frame start signal line, and the second gate driving circuit is coupled to a second frame start signal line;
wherein at least one of the first level signal line, the first clock signal line, the second clock signal line, and the first frame start signal line and the second frame start signal line is made using a second source-drain metal layer in the display substrate; and
wherein at least one of the first level signal line, the first clock signal line, the second clock signal line, the first frame start signal line and the second frame start signal line includes two layers of conductive layers stacked to each other, one layer of conductive layer is made of the second source-drain metal layer, and the other layer of conductive layer is made of a third source-drain metal layer in the display substrate.

2. The display substrate according to claim 1 , wherein the display substrate comprises a display area and a peripheral area surrounding the display area; the plurality of first gate driving circuits and the plurality of second gate driving circuits are all arranged in the peripheral area;
at least part of the first gate driving circuits and at least part of the second gate driving circuits are symmetrically arranged in a peripheral area close to a same side of the display area.

3. The display substrate according to claim 1 , wherein at least part of an orthographic projection of the first level signal line on a base substrate of the display substrate is located between an orthographic projection of the first gate driving circuit on the base substrate and an orthographic projection of the second gate driving circuit on the base substrate.

4. The display substrate according to claim 3 , wherein the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the first gate driving circuit on the base substrate; and/or, the orthographic projection of the first level signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate.

5. The display substrate according to claim 1 , wherein at least part of the first gate driving circuits and at least part of the second gate driving circuits are arranged symmetrically with respect to a first symmetry axis; the first symmetry axis at least partially overlaps the first clock signal line, or the first symmetry axis at least partially overlaps the second clock signal line, or the first symmetry axis at least partially overlaps the first level signal line.

6. The display substrate according to claim 1 , wherein the orthographic projection of the first level signal line on the base substrate is located between an orthographic projection of the first clock signal line on the base substrate and an orthographic projection of the second clock signal line on the base substrate.

7. The display substrate according to claim 1 , wherein the orthographic projection of the first clock signal line on the base substrate at least partially overlaps an orthographic projection of one of the first gate driving circuit and the second gate driving circuit on the base substrate; the orthographic projection of the second clock signal line on the base substrate at least partially overlaps an orthographic projection of the other of the first gate driving circuit and the second gate driving circuit on the base substrate.

8. The display substrate according to claim 1 , wherein the orthographic projection of the first level signal line on the base substrate is located between an orthographic projection of the first frame start signal line on the base substrate and an orthographic projection of the second frame start signal line on the base substrate.

9. The display substrate according to claim 1 , wherein the orthographic projection of the first frame start signal line on the base substrate at least partially overlaps the orthographic projection of the first gate driving circuit on the base substrate;
the orthographic projection of the second frame start signal line on the base substrate at least partially overlaps the orthographic projection of the second gate driving circuit on the base substrate.

10. The display substrate according to claim 1 , wherein the orthographic projection of the first frame start signal line on the base substrate and the orthographic projection of the second frame start signal line on the base substrate are located between the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate.

11. The display substrate according to claim 1 , wherein a width-to-length ratio of a channel of an output transistor included in the first gate driving circuit is equal to or greater than a width-to-length ratio of a channel of an output transistor included in the second gate driving circuit.

12. The display substrate according to claim 1 , wherein the display substrate further includes a plurality of first sub-pixel driving circuits, a plurality of light emitting elements, a plurality of data lines, a plurality of second initialization signal lines and a plurality of third initialization signal lines, the first sub-pixel driving circuit includes a first driving transistor, a first data writing-in transistor, a first compensation transistor, a second reset transistor and a third reset transistor;
a gate electrode of the first data writing-in transistor is coupled to an output terminal of a corresponding first gate driving circuit, and a first electrode of the first data writing-in transistor is coupled to a corresponding data line, and a second electrode of the first data writing-in transistor is coupled to a first electrode of the first driving transistor;
a gate electrode of the first compensation transistor is coupled to the output terminal of the corresponding first gate driving circuit, and a first electrode of the first compensation transistor is coupled to a second electrode of the first driving transistor, a second electrode of the first compensation transistor is coupled to a gate electrode of the first driving transistor;
a gate electrode of the second reset transistor is coupled to an output terminal of a corresponding second gate driving circuit, and a first electrode of the second reset transistor is coupled to a corresponding second initialization signal line, and a second electrode of the second reset transistor is coupled to a corresponding light emitting element;
a gate electrode of the third reset transistor is coupled to the output terminal of the corresponding second gate driving circuit, and a first electrode of the third reset tra

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Miao

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title