Method and architecture for accelerating deterministic stochastic computing using residue number system

Patent metadata

Field	Value
Publication number	US-12307352-B2
Application number	US-202117166378-A
Country	US
Kind code	B2
Filing date	Feb 3, 2021
Priority date	Feb 4, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Inaccuracy of computations is an important challenge with the Stochastic Computing (SC) paradigm. Recently, deterministic approaches to SC are proposed to produce completely accurate results with SC circuits. Instead of random bit-streams, the computations are performed on structured deterministic bit-streams. However, current deterministic methods take a large number of clock cycles to produce correct result. This long processing time directly translates to very high energy consumption. This invention proposes a design methodology based on the Residue Number Systems (RNS) to mitigate the long processing time of the deterministic methods. Compared to the state-of-the-art deterministic methods of SC, the proposed approach delivers improvements in terms of processing time and energy consumption.

First claim

We claim:

1. An architecture for performing bit-stream processing, comprising:
(a) at least one finite state machine;
(b) at least one bit-stream generator;
(c) a moduli set;
(d) at least one input buffer, which stores at least two numbers;
(e) at least one counter;
(f) at least one AND gate;
(g) a controller; and
(h) at least one multiplexer unit;
wherein the stored at least two numbers comprise three residues;
wherein the finite state machines are connected an input of at least one or more multiplexer units;
wherein the stored at least two numbers function as inputs for the architecture;
wherein the stored at least two numbers are stored in Residue Number System format; and
wherein the at least one bit-stream generator comprises coding capable of converting one or more residues of the at least two numbers to bit-stream representation.

2. The architecture of claim 1 , further comprising two or more multiplexer units.

3. The architecture of claim 1 , further comprising at least one multiplexer for each residue to be converted.

4. The architecture of claim 1 , further comprising at least one additional finite state machine, and wherein the finite state machines are configured to generate different low-discrepancy patterns.

5. The architecture of claim 1 , wherein the stored at least two numbers comprise three residues, and further comprising three parallel AND gates where each AND gate is connected to at least one bit-stream generator.

6. The architecture of claim 1 , wherein each of the at least one AND gate is connected to one of the at least one counter.

7. The architecture of claim 1 , wherein the at least one counter stores one or more results of the bit-stream processing.

8. The architecture of claim 1 , further comprising a Reverse Converter.

9. The architecture of claim 1 , further comprising a Reverse Converter comprising a Look-Up Table.

10. A method for performing bit-stream processing, comprising:
storing at least two distinct numbers in an input buffer wherein each distinct number comprises two or more residues;
inputting the at least two distinct numbers into an at least one finite state machine-based bit-stream generator;
generating one or more deterministic bit-streams by the at least one bit-stream generator, wherein each residue conversion comprises use of a separate multiplexer unit;
performing multiplication of one or more outputs of the at least one bit-stream generator using an AND gate to produce a bit-stream;
converting the produced bit-stream to binary representation using a counter; and
calculating any residues.

11. The method of claim 10 , wherein the at least two distinct numbers are stored in Residue Number System format.

12. The method of claim 10 , wherein the converting the produced bit-stream to weighted binary format occurs last.

13. The method of claim 10 , wherein the produced bit-stream is converted to binary representation through the counter counting how many Is are found in the produced bit-stream.

14. The method of claim 10 , further comprising converting the produced bit-stream to weighted binary format.

Assignees

• Univ Louisiana At Lafayette

Inventors

• Najafi Mohammadhassan
• Givaki Kamyar
• Hojabrossadati Seyed Reza
• Gholamrezayi M H
• Khonsari Ahmad
• Gorgin Saeid
• Rahmati Dara

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• H03K19/1737 Primary

  using multiplexers (H03K19/1738 takes precedence) · CPC title

• G06N3/08

  Learning methods · CPC title