Storage device and host device for optimizing model for calculating delay time of the storage device

Patent metadata

Field	Value
Publication number	US-12307127-B2
Application number	US-202418418065-A
Country	US
Kind code	B2
Filing date	Jan 19, 2024
Priority date	Aug 10, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A storage device according to the present technology may include a memory device for storing data, a buffer memory configured to temporarily store data to be stored in the memory device, and a memory controller configured to determine a delay time based on a plurality of parameters upon receipt of a write request from a host, and transmit a data request to the host after the delay time has elapsed.

First claim

What is claimed is:

1. A storage device comprising:
a memory device for storing data;
a buffer memory configured to temporarily store the data that is received by the storage device to be stored in the memory device; and
a memory controller configured to:
determine a delay time based on a sum of values obtained by multiplying a coefficient corresponding to each of a plurality of parameters upon receipt of a write request from a host, and
transmit a data request to the host after the delay time has elapsed.

2. The storage device of claim 1 , wherein the coefficients include values selected through a genetic algorithm in which a latency between a request of an operation to write data and a completion of the operation, and a throughput including a rate at which data is written to the memory device are set as an objective function.

3. The storage device of claim 1 , wherein the plurality of parameters includes usage of the buffer memory and an elapsed time from a time point when the write request is received from the host to a time point when the buffer memory is confirmed to be available, and
upon receipt of the write request from the host, the memory controller transmits a request for state information indicating a memory usage of the buffer memory to the buffer memory, and identifies the usage of the buffer memory and the elapsed time from the state information received from the buffer memory.

4. The storage device of claim 3 , wherein the memory controller increases the delay time as the usage of the buffer memory increases, and decreases the delay time as the elapsed time increases.

5. The storage device of claim 1 , wherein the plurality of parameters include at least two of usage of the buffer memory, an elapsed time from a time point when the write request is received from the host to a time point when the buffer memory is confirmed to be available, a queue depth indicating the number of requests received from the host, and a change per unit time in the usage of the buffer memory.

6. The storage device of claim 1 , wherein the memory controller controls the buffer memory to store data received in response to the data request from the host, controls the memory device to store data stored in the buffer memory according to an operation state of the memory device, and controls the buffer memory to erase the data stored in the buffer memory upon receipt of pass information from the memory device.

Assignees

• Sk Hynix Inc

Inventors

• Kim Ki Tae

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title