PIM computing system and PIM computation offloading method thereof

Patent metadata

Field	Value
Publication number	US-12307093-B2
Application number	US-202218069026-A
Country	US
Kind code	B2
Filing date	Dec 20, 2022
Priority date	Jun 9, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A Processing-In-Memory (PIM) computing system and a PIM computation offloading method thereof perform PIM computation offloading using a DMA engine. The DMA engine is configured to process a transaction by respectively performing descriptor requests and PIM requests for one or more descriptors stored in a memory, in response to a memory request of a CPU. The memory includes a PIM unit and a memory array, which memory array may be a DRAM. In response to the PIM requests, the PIM unit performs PIM operations using information included in data provided to the DMA engine in response to the descriptor requests.

First claim

What is claimed is:

1. A Processing-In-Memory (PIM) computing system comprising:
a central processing unit (CPU) configured to transmit a memory request for offloading of a PIM computation;
a DRAM including a memory array which stores descriptors corresponding to PIM transactions for the PIM computation as descriptors and a PIM device which performs a PIM transaction when the PIM transaction is generated, each of the descriptors including a next descriptor address, operand address information, and an opcode; and
a direct memory access (DMA) engine configured to store a current descriptor address and a tail descriptor address included in the memory request, and sequentially provide a descriptor request and a PIM request for each of the descriptors stored in the DRAM sequentially selected using the first current descriptor address and the last tail descriptor address,
wherein, in response to the descriptor request, the PIM device stores the operand address information and the opcode among descriptor information read from the DRAM by the DMA engine,
wherein, in response to the PIM request, the PIM device performs the PIM transaction by using the stored operand address information and opcode, and
wherein:
the PIM device includes a PIM control register set which includes an operand register, a configuration register and a descriptor register,
descriptor address information provided from the CPU before the PIM computation is started is stored in the descriptor register,
the PIM device identities the descriptor request by comparing a descriptor address selected by the DMA engine for the descriptor request with the descriptor address information stored in the descriptor register, and
the PIM device receives the operand address information and the opcode corresponding to the descriptor address read provided by the DMA engine, and in response to the identified descriptor request, stores the operand address information in the operand register, and stores the opcode in the configuration register.

2. The PIM computing system according to claim 1 , wherein
when the DMA engine provides the PIM request which generates the PIM transaction, the PIM device identifies the PIM request by comparing operand address information provided from the DMA engine for the PIM request with the operand address information stored in the operand register, and
the PIM device executes the PIM transaction according to the opcode stored in the configuration register, in response to the identified PIM request.

3. The PIM computing system according to claim 1 , wherein the PIM device comprises:
a PIM interface unit including a PIM control register set which includes an operand register for registering the operand address information, a configuration register for registering the opcode and a descriptor register for registering descriptor address information, and configured to receive address information and command information and provide a computation control signal; and
a PIM engine configured to perform a computation responding to the descriptor request and the PIM request for the PIM transaction, in response to the computation control signal, and provide a computation result by the PIM request,
wherein the PIM interface unit identifies the command information of the descriptor request and the PIM request by comparing the received address information with the operand address information and the descriptor address information,
wherein, when the descriptor request is identified, the PIM interface unit stores the operand address information among the descriptor information read by the DMA engine, in the operand register, and stores the opcode in the configuration register, and
wherein, when the PIM request is identified, the PIM interface unit provides the computation control signal for execution of the PIM transaction, by using the operand address information stored in the operand register and the opcode stored in the configuration register.

4. The PIM computing system according to claim 3 , wherein the PIM interface unit further includes a switching circuit which forms a data path between the DMA engine and the memory array when the PIM request is identified.

5. A Processing-In-Memory (PIM) computation offloading method of a PIM computing system, the method comprising:
storing a current descriptor address and a tail descriptor address in a DMA engine by transmitting a memory request for offloading of a PIM computation, by a CPU;
before the PIM computation, storing all PIM transactions for the PIM computation as descriptors in a memory array of a DRAM and registering descriptor address information in a PIM device of the DRAM, by the CPU;
sequentially selecting the descriptors from the current descriptor address to the last tail descriptor address for the PIM computation and reading descriptor information by providing a descriptor request for a selected descriptor, by the DMA engine;
providing operand address information and an opcode in the read descriptor information, to the PIM device, by the DMA engine;
identifying the descriptor request and registering the operand address information and the opcode provided from the DMA engine, by the PIM device;
providing a PIM request which generates a PIM transaction, on the basis of the read descriptor information, by the DMA engine;
identifying the PIM request and performing the PIM transaction by using the stored operand address information and opcode, by the PIM device; and
completing the PIM computation by providing the descriptor request and the PIM request for each of the descriptors from the current descriptor address to the last tail descriptor address,
wherein the PIM device identifies the descriptor request by comparing a descriptor address selected by the DMA engine for the descriptor request with the stored descriptor address information.

6. The PIM computation offloading method according to claim 5 , wherein the PIM device identifies the PIM request by comparing operand address information provided from the DMA engine for the PIM request with the stored operand address information.

7. The PIM computation offloading method according to claim 6 , wherein the PIM device executes the PIM transaction according to the stored opcode in response to the identified PIM request.

Assignees

• Sk Hynix Inc
• Univ Korea Res & Bus Found

Inventors

• Kim Seon Wook
• Kim Chang Hyun
• Lee Won Joon

Classifications

• G06F15/7821 Primary

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2213/28

  DMA · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title