Compiler that generates configuration information for configuring an integrated circuit to mitigate inductive-induced voltage droop

Patent metadata

Field	Value
Publication number	US-12306689-B2
Application number	US-202318132393-A
Country	US
Kind code	B2
Filing date	Apr 8, 2023
Priority date	Sep 9, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.

First claim

The invention claimed is:

1. A method, comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
providing the configuration information for use by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit; and
guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations.

2. A method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units; and
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit; and
guarantee that, during execution of the dataflow graph, no more than a predetermined number of the compute units concurrently start to perform the respective operations;

wherein the configuration information comprises a respective group identifier for each of the compute units;
wherein no more than the predetermined number of the compute units are configured with a same group identifier value; and
wherein the group identifier value of each compute unit is comparable with a counter of the compute unit to determine whether the compute unit is permitted to start to perform the respective operations.

3. The method of claim 2 , further comprising:
separating the compute units into N mutually exclusive groups; and
wherein the configuration information comprises a maximum value to which the counter counts, wherein the maximum value is N.

4. A method, comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units; and
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;

wherein the integrated circuit comprises multiple power domains configured to be supplied power by multiple respective power supplies;
wherein the configuration information is usable by the integrated circuit to configure two or more mutually exclusive subsets of the compute units to collectively perform one of the operations; and
wherein configuration information configures the integrated circuit such that the two or more mutually exclusive subsets of the compute units are in two or more mutually exclusive power domains of the multiple power domains such that the two or more mutually exclusive subsets of the compute units are permitted to concurrently start performing the one of the operations.

5. The method of claim 4 ,
wherein the one of the operations comprises a matrix multiply operation performed by the two or more mutually exclusive subsets of the compute units in a systolic manner.

6. A method, comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit having compute units, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
identifying current wavefronts in the dataflow graph;
assigning an identifier of one of the current wavefronts to each of the compute units; and
separating the compute units into mutually exclusive groups based on the current wavefront identifiers;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units; and
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.

7. The method of claim 6 ,
wherein the compute units are arranged as an array within the integrated circuit; and
wherein said separating the compute units into mutually exclusive groups is further based on coordinates of each compute unit within the array.

8. A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit; and
guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations.

9. A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow g

Assignees

• Sambanova Systems Inc

Inventors

• Gandhi Darshan
• Shah Manish K
• Prabhakar Raghu
• Grohoski Gregory Frederick
• Choi Youngmoon
• Shin Jinuk

Classifications

• G06F1/305 Primary

  in the event of power-supply fluctuations · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title