Transistor and display device including the same

Patent metadata

Field	Value
Publication number	US-12302704-B2
Application number	US-202217700195-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Jun 28, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A transistor is disclosed that includes a substrate, an active layer, a gate electrode, a first electrode, a second electrode, and a first connection electrode. The active includes a first region, a second region, and a channel region between the first region and the second region. The gate electrode is disposed on the active layer and overlaps the channel region. The first electrode is disposed on the substrate and electrically connects to the first region. The second electrode is disposed on the substrate and electrically connects to the second region. The first connection electrode is disposed on the substrate and electrically connects the gate electrode and the second electrode.

First claim

What is claimed is:

1. A transistor, comprising:
a substrate;
an active layer disposed on the substrate and including a first region, a second region, and a channel region between the first region and the second region;
a gate electrode disposed on the active layer, the gate electrode overlapping the channel region;
a first electrode disposed on the substrate, the first electrode being electrically connected to the first region;
a second electrode disposed on the substrate, the second electrode being electrically connected to the second region; and
a first connection electrode disposed on the substrate and electrically connecting the gate electrode and the second electrode,
wherein a resistance of the first connection electrode is greater than a resistance of the gate electrode.

2. The transistor of claim 1 , wherein the first connection electrode is disposed at a same layer as the active layer.

3. The transistor of claim 2 , wherein the first connection electrode includes an oxide semiconductor.

4. The transistor of claim 2 , further comprising:
a second connection electrode disposed on the gate electrode, the second connection electrode contacting the first connection electrode and the gate electrode.

5. The transistor of claim 4 , wherein the first connection electrode contacts the second connection electrode and the second electrode.

6. The transistor of claim 4 , wherein the second connection electrode is disposed at a same layer as the second electrode.

7. The transistor of claim 4 , wherein the second connection electrode is disposed on the second electrode.

8. The transistor of claim 2 , further comprising:
a dummy pattern disposed at a same layer as the gate electrode, the dummy pattern overlapping a portion of the first connection electrode.

9. The transistor of claim 8 , wherein an impurity is not doped in the portion of the first connection electrode.

10. The transistor of claim 1 , wherein the first connection electrode is disposed on the second electrode.

11. The transistor of claim 10 , wherein the first connection electrode includes a transparent conductive oxide.

12. The transistor of claim 10 , wherein the first connection electrode contacts the gate electrode and the second electrode.

13. The transistor of claim 10 , further comprising:
a second connection electrode disposed at a same layer as the second electrode, the second connection electrode contacting the gate electrode and the first connection electrode.

14. The transistor of claim 13 , wherein the first connection electrode contacts the second connection electrode and the second electrode.

15. A display device, comprising:
a display portion including a substrate and a plurality of pixels disposed on the substrate;
a driver configured to provide a driving signal to the display portion;
a controller configured to provide a control signal to the driver; and
a transistor connected to a connection line connecting the display portion and the driver or connecting the driver and the controller, the transistor including:
an active layer disposed on the substrate and including a first region, a second region, and a channel region between the first region and the second region;
a gate electrode disposed on the active layer, the gate electrode overlapping the channel region;
a first electrode disposed on the substrate, the first electrode being electrically connected to the first region;
a second electrode disposed on the substrate, the second electrode being electrically connected to the second region; and
a first connection electrode disposed on the substrate, the first connection electrode electrically connecting the gate electrode and the second electrode,
wherein a resistance of the first connection electrode is greater than a resistance of the gate electrode.

16. The display device of claim 15 , wherein one of the first electrode and the second electrode is connected to the connection line, and
wherein the other of the first electrode and the second electrode is connected to a power voltage line configured to provide a power voltage to the plurality of pixels.

17. The display device of claim 15 , wherein each of the plurality of pixels includes:
a pixel electrode disposed on the second electrode;
an emission layer disposed on the pixel electrode; and
an opposite electrode disposed on the emission layer.

18. The display device of claim 17 , wherein the transistor further includes:
a second connection electrode disposed on the gate electrode, the second connection electrode contacting the first connection electrode and the gate electrode.

19. The display device of claim 18 , wherein the first connection electrode is disposed at a same layer as the active layer, and
wherein the second connection electrode is disposed at a same layer as the second electrode.

20. The display device of claim 18 , wherein the first connection electrode is disposed at a same layer as the active layer, and
wherein the second connection electrode is disposed at a same layer as the pixel electrode.

21. The display device of claim 18 , wherein the first connection electrode is disposed at a same layer as the pixel electrode, and
wherein the second connection electrode is disposed at a same layer as the second electrode.

22. The display device of claim 17 , wherein the first connection electrode is disposed at a same layer as the pixel electrode.

23. The display device of claim 15 , wherein the first connection electrode is disposed at a same layer as the active layer or on the second electrode.

Assignees

• Samsung Display Co Ltd

Inventors

• Jung Hyunggi
• Son Yongduck
• Yeon Soon Chang
• Yoo Younghoon
• Lee Jaemin
• Lim Dogi
• Jeong Soojin
• Jung Hyungtae

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6723

  having light shields · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title