Automatic self checking and healing of physically unclonable functions

Patent metadata

Field	Value
Publication number	US-12301737-B2
Application number	US-202218264369-A
Country	US
Kind code	B2
Filing date	Feb 4, 2022
Priority date	Feb 4, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A method and circuit for an Automatic Self Checking and Healing (ASCH) of Physically Unclonable Functions (PUFs), the method includes: controlling a skew input added to each PUF cell of a PUF array in a circuit with sub-mV resolution; healing a portion of unstable bits of each PUF cells locally; and performing a second self-checking on healed PUF cells to determine final PUF cells to discard. The method further includes performing at least one of a static operation mode, a dynamic operation mode, and a hybrid operation mode of ASCH stabilization system based on design needs to reconfigure and mask the PUF array to achieve less than 1E-8 Bit Error Rate (BER) with less than 25% masking ratio. The circuit includes the skew input, a self-checking controller, a high-speed readout, a validity detector, and a Digital-to-Analog Converter (DAC). Further, each PUF cell in the PUF array is an inverter-based PUF and includes a first stage inverter and a second stage inverter such that the second stage inverter includes other stages except the first stage inverter.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A method for an Automatic Self Checking and Healing (ASCH) of Physically Unclonable Functions (PUFs), the method comprising:
controlling a skew input added to each PUF cell of a PUF array in a circuit with sub-mV resolution;
healing a portion of unstable bits of each PUF cells locally;
performing a second self-checking on healed PUF cells to determine final PUF cells to discard; and
performing at least one of a static operation mode, a dynamic operation mode, and a hybrid operation mode of ASCH stabilization system based on design needs to reconfigure and mask the PUF array to achieve less than 1E-8 Bit Error Rate (BER) with less than 25% masking ratio,
wherein the circuit comprises the skew input, a self checking controller, a high-speed readout circuit, a validity detector, and a Digital-to-Analog Converter (DAC), and
wherein each PUF cell in the PUF array is an inverter-based PUF and includes a first stage inverter and a second stage inverter such that the second stage inverter comprising other stages except the first stage inverter.

2. The method as set forth in claim 1 , wherein in the static operation mode, ASCH is used during enrollment phase and generates a static mask based on the skew input, and remains active once the PUF array is put to use.

3. The method as set forth in claim 1 , wherein in the dynamic operation mode, ASCH is not used during enrollment, but is used every time the PUF array start-up to get an in-field dynamic mask and the dynamic mask is stored temporarily on registers.

4. The method as set forth in claim 1 , wherein in the hybrid operation mode, ASCH is used both during enrollment and during the PUF array start-up, combining the static mask and the dynamic mask to achieve the minimum masking ratio for “0” BER across an entire temperature range by carefully selecting two skew parameters.

5. The method as set forth in claim 1 , wherein to achieve sub-mV accuracy, the ASCH stabilization system employs a two-step locking process with a coarse binary exhaustive search and a fine linear search by dithering a DAC output with a 4-bit Pulse Width Modulation (PWM) to achieve a 12-bit resolution, and
wherein after locking, two consecutive PUF evaluation sessions are performed and all PUF cells that ever flip once during the two sessions are marked as unstable by a validity checker.

6. The method as set forth in claim 1 , further comprising:
implementing auto-zeroing and averaging comparator outputs across a configurable moving window to reduce comparison mismatch and noise.

7. The method as set forth in claim 1 , wherein a first capacitor and a second capacitor are added to the circuit to stabilize a dithered voltage.

8. The method as set forth in claim 1 , wherein a dark bit detection accuracy is dependent on the number of PUF evaluation sessions during self-checking.

9. A circuit for an Automatic Self Checking and Healing (ASCH) of Physically Unclonable Functions (PUFs), the circuit comprising:
a PUF cell;
a self-checking controller;
a validity detector for automatic detection of unstable cells by checking stability of the PUF cell based on an evaluated PUF bit;
an 8-bit resistive Digital-to-Analog Converter (DAC);
an auto-zeroing comparator;
a skew input;
a timing control;
a power rail;
a ground rail;
a plurality of pMOSFET (Metal Oxide Semiconductor Field Effect Transistor); and
a plurality of nMOSFET,
wherein the PUF cell further comprising a first stage inverter and a second stage inverter, and
wherein the second stage inverter comprising other stages except the first stage inverter.

10. The circuit as set forth in claim 9 , further comprising a SRAM-like peripheral integrated for high-speed parallel readout to sample and output a PUF value at every rising clock edge from the timing control.

11. The circuit as set forth in claim 9 , further comprising a plurality of NOR gates and multiple D-flip flops (FF), wherein the validity detector outputs a “1” from either of the D-FF if there is a PUF transition and outputs a “0” from the plurality of NOR gates if the evaluated PUF bit value is unstable.

12. The circuit as set forth in claim 9 , further comprising supply voltages of each PUF cell's first stage and other stages and an external source, wherein the supply voltage of each PUF cell's first stage is controlled by the 8-bit DAC and the auto-zeroing comparator.

13. The circuit as set forth in claim 9 , further comprising a coarse-fine locking process added before the skew input and the validity detector to enable self-checking using the self-checking controller.

14. The circuit as set forth in claim 9 , further comprising a first capacitor, and a second capacitor to stabilize a dithered voltage resulted from a DAC value being dithered using a 4-bit pulse width modulation.

15. A non-transitory computer readable medium storing instructions, the instructions executable by a computer processor using a core numerical algorithm and comprising functionality for:
controlling a skew input added to each PUF cell of a PUF array with sub-mV resolution;
healing a portion of unstable bits of each PUF cells locally;
performing a second self-checking on healed PUF cells to determine final PUF cells to discard; and
performing at least one of a static operation mode, a dynamic operation mode, and a hybrid operation mode of Automatic Self Checking and Healing (ASCH) stabilization system based on design needs to reconfigure and mask the PUF array to achieve less than 1E-8 Bit Error Rate (BER) with less than 25% masking ratio.

Assignees

• Univ Rice William M

Inventors

• Yang Kaiyuan
• He Yan

Classifications

• H04L2209/26

  Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm · CPC title

• G01R35/005

  Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence) · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title