Methods and apparatus to improve differential non-linearity in digital to analog converters

Patent metadata

Field	Value
Publication number	US-12301244-B2
Application number	US-202418748371-A
Country	US
Kind code	B2
Filing date	Jun 20, 2024
Priority date	Sep 22, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

First claim

What is claimed is:

1. A device, comprising:
a set of resistors coupled in series, each resistor including a first terminal and a second terminal;
a first set of switches, each switch including a first terminal and a second terminal, the first terminal of each switch coupled to the first terminal of a corresponding resistor of the first set of resistors, the first set of switches segmented into subsets of switches, and the second terminals of switches in each subset coupled altogether to provide a respective first joint terminal;
a second set of switches, each switch including a first terminal and a second terminal,
the first terminal of each switch coupled to the respective first joint terminal of a corresponding subset of the first set of switches, and the second terminals of switches of the second set of switches coupled altogether to provide a second joint terminal; and

decoder circuitry configured to:
receive digital data; and
control the first set of switches and the second set of switches based on the digital data to provide a voltage at the second joint terminal.

2. The device of claim 1 , wherein the decoder circuitry is configured to:
control the first set of switches based on an entirety of the digital data; and
control the second set of switches based on a partial portion of the digital data.

3. The device of claim 2 , wherein the partial portion corresponds to one or more most significant bits of the digital data.

4. The device of claim 3 , wherein a number of switches in the first set of switches is equal to a number of bits of the digital data.

5. The device of claim 4 , wherein a number of subsets in the first set of switches and a number of switches in the second set of switches are equal to a number of the one or more most significant bits of the digital data.

6. The device of claim 1 , wherein the decoder circuitry is configured to:
control one switch in each subset of the first set of switches as a group, such that the switches in each group are open or closed altogether.

7. The device of claim 6 , wherein the decoder circuitry is configured to:
close one group of switches of the first set of switches; and
open a remainder of the first set of switches.

8. The device of claim 1 , wherein the decoder circuitry is configured to:
close one switch of the second set of switches; and
open a remainder of the second set of switches.

9. The device of claim 1 , wherein the set of resistors has one same resistance value.

10. The device of claim 1 , wherein the set of resistors is configured to collectively receive an input voltage.

11. A device, comprising:
processor circuitry configured to provide digital data;
digital-to-analog converter (DAC) circuitry comprising:
a set of resistors coupled in series, each resistor including a first terminal and a second terminal;
a first set of switches, each switch including a first terminal and a second terminal, the first terminal of each switch coupled to the first terminal of a corresponding resistor of the first set of resistors, the first set of switches segmented into subsets of switches, and the second terminals of switches in each subset coupled altogether to provide a respective first joint terminal;
a second set of switches, each switch including a first terminal and a second terminal, the first terminal of each switch coupled to the respective first joint terminal of a corresponding subset of the first set of switches, and
the second terminals of switches of the second set of switches coupled altogether to provide a second joint terminal; and

decoder circuitry configured to:
receive the digital data; and
control the first set of switches and the second set of switches based on the digital data to provide a voltage at the second joint terminal; and

transmitter circuitry configured to transmit the voltage.

12. The device of claim 11 , wherein the decoder circuitry is configured to:
control the first set of switches based on an entirety of the digital data; and
control the second set of switches based on a partial portion of the digital data.

13. The device of claim 12 , wherein the partial portion corresponds to one or more most significant bits of the digital data.

14. The device of claim 13 , wherein a number of switches in the first set of switches is equal to a number of bits of the digital data.

15. The device of claim 14 , wherein a number of subsets in the first set of switches and a number of switches in the second set of switches are equal to a number of the one or more most significant bits of the digital data.

16. The device of claim 11 , wherein the decoder circuitry is configured to:
control one switch in each subset of the first set of switches as a group, such that the switches in each group are open or closed altogether.

17. The device of claim 16 , wherein the decoder circuitry is configured to:
close one group of switches of the first set of switches; and
open a remainder of the first set of switches.

18. The device of claim 17 , wherein:
the digital data includes 4 bits corresponding to 16 binary values;
the first set of switches includes 16 switches, and each subset of the first set of switches includes 4 switches; and
the decoder circuitry is configured to:
based on the digital data being equal to each one of 4 binary values of the 16 binary values,
close a first switch in a first subset, a second switch in a second subset,
a third switch in a third subset, and a fourth switch in a fourth subset altogether as a group; and

open a remainder of the first set of switches.

19. The device of claim 11 , wherein the decoder circuitry is configured to:
close one switch of the second set of switches; and
open a remainder of the second set of switches.

20. The device of claim 19 , wherein:
the digital data includes 4 bits corresponding to 16 binary values;
the second set of switches includes 4 switches; and
the decoder circuitry is configured to:
based on the digital data being equal to each one of 4 binary values of the 16 binary values,
close a first switch of the second set of switches; and
open a remainder of the second set of switches.

Assignees

• Texas Instruments Inc

Inventors

• Elies Brian

Classifications

• H03M1/80

  using weighted impedances (H03M1/76 takes precedence) · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M3/00

  Conversion of analogue values to or from differential modulation · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/76

  using switching tree · CPC title